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• About RPT

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• About IVM

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• About CDIF

The Connected Dataflow Idiom Finder is a stand-alone tool for extracting common dataflow idioms out of a sequence of code regions. It performs an exhaustive analysis, building all possible subgraphs in order to find those which best meet the selection criteria. It also allows the user to fine-tune what defines a legal idiom by applying restrictions from a number of possible constraints. CDIF is highly parameterizable and is immediately useful for a number of potential applications.

See this page for more details.

The rePLay Transmogrifier is a general purpose instruction decoder that transforms specific ISA instruction streams into into generic micro-operations with the goal of realisticly modeling a modern micro-processor's decoder translations. This release sports general improvements to the interface and core code to allow users quicker understanding.

See this page for more details.

The Illinois Verilog Model (IVM) is a Verilog implementation of an Alpha microprocessor. The microarchitecture is a superscalar, dynamically scheduled pipeline, executing a subset of the Alpha instruction set. The processor includes such features as speculative instruction scheduling, memory dependence prediction, and sophosticated branch prediction. Up to 132 instructions can be in-flight in the 12-stage pipeline. Not including the caches and predictor tables, the processor core consists of approximately 50,000 bit elements of state (pipeline latches and RAM storage).

See this page for more details.

The rePLay Transmogrifier is a general purpose instruction decoder that transforms specific ISA instruction streams into into generic micro-operations with the goal of realisticly modeling a modern micro-processor's decoder translations. The RPT infrastructure supports the execution of the micro-operations along with support for checking the resulting state with the corresponding architectural reference model. The interface for the transmogrifier can be plugged into any number of specific ISA reference models, emulators, or trace generators suchs as bochs, simics, or shade (assuming a minimal interface is established). The resulting micro-op's can be used to accomodate a variety of custom timing model infrastructures for the purposes of simulation.

See this page for more details.

The Advanced Computing Systems research group is very excited to bring you the new ACS Tools Webpage. We have worked very hard building up our simulation infrastructure over the last few years, and we would like to share some of our tools with the research community. The primary goal of this project is to help enable other computer architecture and related researchers by providing powerful simulation tools in the hopes that these tools can be co-developed, verified, and maintained by a wide audience.

Please have a look around and feel free to send any comments to slechta@crhc.uiuc.edu.

For those of you who are wondering why some of the pages are still incomplete, please be patient. There will be a lot of updates over the next few weeks.