PUBLICATIONS

E. S. Davidson, L. E. Shar, A. T. Thomas and J. H. Patel, "Effective Control for Pipelined Computers, "Proc. COMPCON Spring '75, pp. 181-184, Feb. 1975.

J. H. Patel and E. S. Davidson, "Improving the Throughput of a Pipeline by Insertion of Delays," Proc. 3rd Annual Symp. on Computer Architecture, pp. 159-164, Jan. 1976.

J. H. Patel, "Pipelines with Internal Buffers," Proc. 5th Annual Symp. on Computer Architecture, pp. 249-254, April 1978.

J. H. Patel, "Performance Studies of Internally Buffered Pipelines," Proc. 1978 Int. Conf. on Parallel Processing, pp. 36-42, Aug. 1978.

J. H. Patel, "Processor-Memory Interconnections for Multiprocessors," Proc. 6th Annual Symp. on Computer Architecture, pp. 168-177, April 1979.

F. A. Briggs, K. S. Fu, K. Hwang and J. H. Patel, "PM4-A Reconfigurable Multiprocessor System for Pattern Recognition and Image Processing," AFIPS-Conf. Proc., vol. 48, pp. 255-265, 1979.

J. H. Patel, "An Alternative to the Distributed Pipeline," IEEE Trans. on Computers, vol. C-29, pp. 736-737, Aug. 1980.

J. H. Patel, "A Performance Model for Multiprocessors with Private Cache Memories," Proc. 1981 Int. Conf. on Parallel Processing, pp. 314-317, Aug. 1981.

J. H. Patel, "Performance of Processor-Memory Interconnections for Multiprocessors," IEEE Trans. on Computers, vol. C-30, pp. 771-780, Oct. 1981.

F. A. Briggs, K. S. Fu, K. Hwang and J. H. Patel, "A Shared-Resource Multiple Microprocessor System for Pattern Recognition and Image Processing," in Special Computer Architectures for Pattern Processing, K. S. Fu, Editor, CRC Press: Boca Raton, Florida, pp. 221-238, 1982.

J. H. Patel, "Analysis of Multiprocessors with Private Cache Memories," IEEE Trans. on Computers, vol. C-31, pp. 296-304, April 1982.

J. H. Patel and L. Y. Fung, "Multiplier and Divider Arrays with Concurrent Error Detection," Proc. 1982 Int. Symp. on Fault-Tolerant Computing, pp. 325-329, June 1982.

J. H. Patel and L. Y. Fung, "Concurrent Error dDetection in ALUs by Recomputing with Shifted Operands," IEEE Trans. on Computers, vol. C-31, pp. 589-595, July 1982.

G. F. Grohoski and J. H. Patel, "A Performance Model for Instruction Prefetch in Pipelined Instruction Units," Proc. 1982 Int. Conf. on Parallel Processing, pp. 248-252, Aug. 1982.

A. J. Kessler and J. H. Patel, "Reconfigurable Parallel Pipelines for Fault Tolerance," Proc. IEEE Int. Conf. on Circuits and Computers, pp. 118-121, Sept. 1982.

J. H. Patel, "Application of Time-Redundancy to Fault-Tolerance," Proc. National Electronics Conf., vol. 36, pp. 340-345, Oct. 1982 (invited paper).

D. W-L. Yen, J. H. Patel and E. S. Davidson, "Memory Interference in Synchronous Multiprocessor Systems," IEEE Trans. on Computers, vol. C-31, pp. 1116-1121, Nov. 1982.

P. C-C. Yeh, J. H. Patel and E. S. Davidson, "Shared Cache for Multiple-Stream Computer Systems," IEEE Trans. on Computers, vol. C-32, pp. 38-47, Jan. 1983.

J. H. Patel and L. Y. Fung, "Concurrent Error Detection in Multiply and Divide Arrays," IEEE Trans. on Computers, vol. C-32, pp. 417-422, April 1983.

P. C. C. Yeh, J. H. Patel and E. S. Davidson, "Performance of Shared Cache for Parallel-Pipelined Computer Systems," Proc. 10th Int. Symp. on Computer Architecture, pp. 117-123, June 1983.

S. Laha and J. H. Patel, "Error Correction in Arithmetic Operations Using Time Redundancy," Proc. 13th Int. Symp. on Fault-Tolerant Computing, pp. 298-305, June 1983.

L. H. Pollard and J. H. Patel, "Correction of Errors in Data Transmission Using Time Redundancy," Proc. 13th Int. Symp. on Fault-Tolerant Computing, pp. 314-317, June 1983.

J. A. Abraham, E. S. Davidson and J. H. Patel, "Memory System Design for Tolerating Single Event Upsets," IEEE Trans. on Nuclear Science, vol. NS-30, no. 6, pp. 4339-4344, Dec. 1983.

M. S. Papamarcos and J. H. Patel, "A Low-Overhead Coherence Solution for Multiprocessors With Private Cache Memories," Proc. 11th Annual Int. Symp. on Computer Architecture, pp. 348-354, June 1984.

W-T. Cheng and J. H. Patel, "Concurrent Error Detection in Iterative Logic Arrays," Proc. 14th Int. Symp. on Fault-Tolerant Computing, pp. 10-15, June 1984.

L. H. Pollard and J. H. Patel, "Fault-Tolerant Techniques for Control Signals in Bus Communication Protocols," Proc. 14th Int. Symp. on Fault-Tolerant Computing, pp. 380-385, June 1984.

J. H. Patel, "Built-In-Test for Bit-Sliced ALU," Proc. Int. Conf. on Computer Design (ICCD '84) ,pp. 308-312, Oct. 1984.

R. Dandapani, J. H. Patel and J. A. Abraham, "Design of Test Pattern Generators for Built-In-Test," Proc. Int. Test Conf., pp. 315-319, Oct. 1984.

G. S. Sohi, E. S. Davidson, and J. H. Patel, "An Efficient LISP-Execution Architecture With a New Representation for List Structures, "Proc. 12th Int. Symp. on Computer Architecture, pp. 91-97, June 1985.

A. Ram and J. H. Patel, "Parallel Garbage Collection Without Synchronization Overhead, "Proc. 12th Int. Symp. on Computer Architecture, pp. 84-90, June 1985.

W-T. Cheng and J. H. Patel, "A Minimum Test Set for Multiple-Fault Detection in Ripple Carry Adders, "Proc. Int. Conf. on Computer Design (ICCD '85), pp. 435-438, Oct. 1985.

R. J. Eickemeyer and J. H. Patel, "A Parallel Stack Processor (PSP), "Proc. Int. Conf. on Computer Design (ICCD '85), pp. 473-476, Oct. 1985.

W-T. Cheng and J. H. Patel, "Multiple-Fault Detection in Iterative Logic Arrays, "Proc. Int. Test Conf., pp. 493-499, Nov. 1985.

W-T. Cheng and J. H. Patel, "A Shortest Length Test Sequence for Sequential-Fault Detection in Ripple Carry Adders, "Proc. Int. Conf. on Computer-Aided Design,(ICCAD-85), pp. 71-73, Nov. 1985.

M. Sharma, J. H. Patel, and N. Ahuja, "NETRA: An Architecture for a Large Scale Multiprocessor Vision System," Proc. IEEE Comp. Soc. Workshop on Computer Architecture for Pattern Analysis and Image Data Base Management, pp. 92-98, Nov. 1985.

M. Malkawi and J. H. Patel, "Compiler Directed Memory Management Policy for Numerical Programs," Proc. ACM SIGOPS 10th Symp. on Op. Sys. Principles, pp. 97-106, Dec. 1985.

M. Malkawi and J. H. Patel, "Performance Measurement of Paging Behavior in Multiprogramming Systems," Proc. 13th Int. Symp. on Computer Architecture, pp. 111-118, June 1986.

W.-T. Cheng and J. H. Patel, "Testing in Two-Dimensional Iterative Logic Arrays," Proc. 16th Int. Symp. on Fault-Tolerant Computing, pp. 76-81, July 1986.

S. Patel and J. H. Patel, "Effectiveness of Heuristics Measures for Automatic Test Pattern Generation," Proc. 23rd Design Automation Conf., pp. 547-552, July 1986.

W.-T. Cheng and J. H. Patel, "Testing in Two-Dimensional Iterative Logic Arrays," Int. Journal of Computers and Mathematics with Applications, vol. 13, no. 5/6, pp. 443-454, Jan. 1987.

R. J. Eickemeyer and J. H. Patel, "Performance Evaluation of Multiple Register Sets," Proc. 14th Annual Symp. on Computer Architecture, pp. 264-271, June 1987.

S. J. Chandra and J. H. Patel, "A Hierarchical Approach to Test Vector Generation," Proc. 24th ACM/IEEE Design Automation Conf., pp. 495-501, June 1987.

P. Mazumder and J. H. Patel, "Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories," Proc. 24th ACM/IEEE Design Automation Conf., pp. 688-694, June 1987.

P. Mazumder and J. H. Patel, "Methodologies for Testing Embedded Content Addressable Memories," Proc. 17th Int. Symp. on Fault-Tolerant Computing, pp. 270-275, July 1987.

W.-T. Cheng and J. H. Patel, "A Minimum Test Set for Multiple-Fault Detection in Ripple-Carry Adders," IEEE Trans. on Computers, vol. C-36, pp. 891-895, July 1987.

M. Sharma, N. Ahuja, J.H. Patel, "NETRA:  An Architecture for a Large Scale Multiprocessor Vision System," in Parallel Computer Vision, Leonard Uhr, Editor, Academic Press:  Orlando, Florida, pp. 87-107, 1987.

S. G. Abraham and J. H. Patel, "Parallel Garbage Collection on a Virtual Memory System," Proc. 1987 Int. Conf. on Parallel Processing, pp. 243-246, Aug. 1987.

J. A. Abraham, G. Metze, R. K. Iyer and J. H. Patel, "The Evolution of Fault-Tolerant Computing at the University of Illinois," in The Evolution of Fault-Tolerant Computing,Springer-Verlag, pp. 271-288, 1987.

P. Mazumder and J. H. Patel, "An Efficient Built-in Self Testing for Random Access Memory," Int. Test Conf., pp. 1072-1077, Sept. 1987.

P. Mazumder and J. H. Patel, "A Novel Fault-Tolerant Design of Testable Dynamic Random Access Memory," Proc. Int. Conf. on Computer Design (ICCD '87), pp. 306-309, Oct. 1987.

P. Mazumder, J. H. Patel and W. K. Fuchs, "Methodologies for Testing Embedded Content Addressable Memories," IEEE Trans. on Computer-Aided Design, vol. 7, pp. 11-20, Jan. 1988.

P. Mazumder and J. H. Patel, "Parallel Testing of Parametric Faults in a DRAM," Proc. Advanced Research in VLSI: 5th MIT Conf., pp. 148-160, Mar. 1988.

R. J. Eickemeyer and J. H. Patel, "Performance Evaluation of on-Chip Register and Cache Organizations," Proc. 15th Int. Annual Symp. on Computer Architecture, pp. 64-72, May 1988.

A. M. Saleh and J. H. Patel, "Transient-Fault Analysis for Retry Techniques," IEEE Trans. on Reliability, vol. 37, no. 3, pp. 323-330, Aug. 1988.

A. N. Choudhary and J. H. Patel, "A Parallel Architecture for an Integrated Vision System,"Proc. 17th Int. Conf. on Parallel Processing, pp. 383-387, Aug. 1988.

S. J. Chandra and J. H. Patel, "Test Generation in a Parallel Processing Environment," Proc. Int. Conf. on Computer-Design, pp. 11-14, Oct. 3-5, 1988.

J. A. Abraham, D. S. Brahme, S. J. Chandra, A. Chatterjee, and J. H. Patel, "Speedup of Test Generation Through Use of High Level Knowledge," TECHCON '88, pp. 145-148, Oct. 1988.

A. N. Choudhary and J. H. Patel, "Performance of Integrated Image Understanding Benchmarks on NETRA:  A Parallel Architecture for Integrated Vision Systems," Image Understanding Benchmark Workshop, Oct. 1988.

S. Laha, J. H. Patel and R. K. Iyer, "Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems," IEEE Trans. on Computers, vol. 37, no. 11, pp. 1325-1336, Nov. 1988.

M.-F. Chang, W. K. Fuchs, and J. H. Patel, "Diagnosis and Repair of Memory with Coupling Faults," Proc. Int. Conf. on Computer Aided-Design (ICCAD), pp. 524-527, Nov. 1988.

R. K. Roy, T. M. Niermann, J. H. Patel, J. A. Abraham, and R. A. Saleh, "Compaction of ATPG-Generated Test Sequences for Sequential Circuit," Proc. Int. Conf. on Computer-Aided Design (ICCAD), pp. 382-384, Nov. 1988.

S. J. Chandra and J. H. Patel, "Experimental Evaluation of Testability Measures for Test Generation," IEEE Trans. on Computer-Aided Design, vol. 8, no. 8, pp. 93-97, Jan. 1989.

M. K. Leung, A. N. Choudhary, J. H. Patel and T. S. Huang,"Point Matching in a Time Sequence of Stereo Image Pairs and Its Parallel Implementation on a Multiprocessor," IEEE Workshop on Visual Motion, pp. 321-328, Mar. 1989.

A. N. Choudhary, S. Das, N. Ahuja and J. H. Patel, "Surface Reconstruction from Stereo Images: an Implementation on a Hypercube Multiprocessor," The Fourth Conf. on Hypercube Concurrent Computers and Applications, Monterey, CA., pp. 1045-1053, Mar. 1989.

P. Mazumder and J. H. Patel, "Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories," IEEE Trans. on Computers, vol. 38. no. 3, pp. 394-407, Mar. 1989.

M.-F. Chang, W. K. Fuchs and J. H. Patel, "Diagnosis and Repair of Memory with Coupling Faults," IEEE Trans. on Computers, vol. 38, no. 4, pp. 493-500, April 1989.

U. J. Davé and J. H. Patel, "A Functional-Level Test Generation Methodology Using Two-Level Representations," 26th ACM/IEEE Design Automation Conf., pp. 722-725, June 1989.

W. K. Fuchs, W. Page, J. H. Patel, and P. Tobin, "Workstation-Based Logic Animation and Microarchitecture Emulation for Teaching Introduction to Computer Engineering," IEEE Trans. on Education, vol. 32, no. 3, pp. 218-225, Aug. 1989.

K.-L. Wu, W. K. Fuchs, and J. H. Patel, "Cache-Based Error Recovery for Share Memory Multiprocessor Systems," 1989 Int. Conf. on Parallel Processing, vol. I, pp. 159-166, Aug. 1989.

J. Baxter and J. H. Patel, "The LAST Algorithm: A Heuristic-Based Static Task Allocation Algorithm," 1989 Int. Conf. on Parallel Processing, vol. II, pp. 217-222, Aug. 1989.

S. J. Chandra and J. H. Patel, "Accurate Logic Simulation in the Presence of Unknowns," Proc. Int. Conf. on Computer-Aided Design (ICCAD), pp. 34-37, Nov. 1989.

A. N. Choudhary and J. H. Patel, "Load Balancing and Task Decomposition Techniques for Parallel Implementation of Integrated Vision Systems Algorithms," Proc. Supercomputing 1989, pp. 266-275, 1989.

W-T. Cheng and J. H. Patel, "Proofs: A Super Fast Fault Simulator for Sequential Circuits," Proc. IEEE European Design Automation Conf., Glasgow, Scotland, pp. 475-479, Mar. 1990.

A.M. Saleh, J. J. Serano, and J. H. Patel, "Reliability of Scrubbin Recovery-Techniques for Memory Systems," IEEE J. Trans. Reliability, vol. 39, no. 1, pp. 114-122, Apr. 1990.

K-L. Wu, W. K. Fuchs, and J. H. Patel, "Error Recovery in Shared Memory Multiprocessors Using Private Caches," IEEE Trans. Parallel/Distributed Sys., vol. 1, no. 2, pp.231-241, Apr. 1990.

P. Mazumder, J. H. Patel, and J. A. Abraham, "A Reconfigurable Parallel Signature Analyzer for Concurrent Error Correction in DRAM," IEEE Solid-State Circuits, vol. 25, no. 3, pp. 866-870, June, 1990.

A. N. Choudhary, S. Das, N. Ahuja, and J. H. Patel, "A Reconfigurable and Hierarchical Parallel Processing Architecture: Performance Results for Stereo Vision," Proc. 10th Int. Conf. Pattern Recognition, Atlantic City, NJ, pp. 389-393, June, 1990.

A. N. Choudhary, M. K. Leung, T. S. Huang, and J. H. Patel, "Parallel Implementation and Evaluation of Motion Estimation System Algorithms on a Distributed Memory Multiprocessor Using Knowledge Based Mappings," Proc. 10th Int. Conf. Pattern Recognition, Atlantic City, NJ, pp. 337-342, June 1990.

T. M. Niermann, W. Cheng, and J. H. Patel, "PROOFS: A Fast Memory Efficient Sequential Circuit Fault Simulator," IEEE Proc. 27th Design Automation Conf., pp. 535-540, July 1990.

A. N. Choudhary and J. H. Patel, "Performance Evaluation of Clusters of NETRA: An Architecture for Computer Vision Systems," Proc. Int. Conf. Parallel Processing, St. Charles, IL, vol. 1, pp. 494-497, Aug. 1990.

V. Chickermane and J. H. Patel, "An Optimization Based Approach to the Partial Scan Design Problem," Int. Test Conf., Washington, DC, pp. 377-386, Sept. 1990.

T. M. Niermann and J. H. Patel, "HITEC/PROOFS A Test Generation and Fault Simulation System," SRC Techcon 90, San Jose, CA, pp. 391-394, Oct. 1990.

R. K. Iyer, J. H. Patel, W. K. Fuchs, P. Banerjee, and R. Horst, Chapter in "Hardware and SoftwareFault Tolerance," Chapter in "Encyclopedia of Microcomputers" vol. 8, pp. 161-200, 1991.

A. Chatterjee, R. K. Roy, J. A. Abraham, and J. H. Patel, "Efficient TestingTechniques for Bit and Digit-Serial Arrays," 4th Int. Symp. on VLSI Design, New Delhi, India, pp. 142-147, Jan. 1991.

T. Niermann and J. H. Patel, "HITEC: A Test Generation Package for Sequential Circuits," European Design Automation Conf., Amsterdam, Netherlands, pp. 214-218, Feb. 1991.

J. W. C. Fu and J. H. Patel, "Data Prefetch Strategies for Vector Cache Memories," Proc. 5th Int. Parallel Processing Symp., Anaheim, CA., pp. 555-561, May 1991.

J. W. C. Fu and J. H. Patel, "Data Prefetching in Multiprocessor Vector Cache Memories," 18th Annual Int. Symp. on Computer Architecture, Toronto, Canada, pp. 54-64, May 1991.

S. Patil, P. Banerjee, and J. H. Patel, "Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors," 28th Design Automation Conf., San Francisco, CA, pp. 155-159, June 17-21, 1991.

J. Lee and J. H. Patel, "An Architectural Level Test Generator for a Hierarchical Design Environment," Int. Symp. on Fault-Tolerant Computing, (FTCS), Montreal, Canada, pp. 44-51, June 25-27, 1991.

A. N. Choudhary, J. H. Patel, and N. Ahuja, "Architecture and Performance Evaluation of NETRA," Chapter in "Parallel Architectures and Algorithms for Image Understanding" ,

edited by V. K. Prasanna Kumar, Academic Press, New York, NY, pp. 251-279, July, 1991.

J. Lee and J. H. Patel, "ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults," Proc. Int. Test Conf. (ITC), Nashville, TN, pp. 729-739, Oct. 1991.

A. Chatterjee, R. K. Roy, J. A. Abraham, and J. H. Patel, "Efficient Testing Strategies for Bit-and Digit-Serial Arrays Used in Digital Signal Processors," Digital Signal Processing, vol. I, pp. 231-244, 1991.

J. Lee and J. H. Patel, "A Signal-driven Discrete Relaxation Technique for Architectural Level Test Generation," Proc. Int. Conf. on Computer-Aided Design (ICCAD-91), Santa Clara, CA, pp. 458-462, Nov. 1991.

V. Chickermane and J. H. Patel, "A Fault Oriented Partial Scan Design Approach," Proc. Int. Conf. on Computer-Aided Design (ICCAD-91), Santa Clara, CA, pp. 400-404, Nov. 1991.

E. Rudnick, T. M. Niermann, and J. H. Patel, "Methods for Reducing Events in Sequential Circuit Fault Simulation," Proc. Int. Conf. on Computer-Aided Design (ICCAD-91), Santa Clara, CA, pp. 546-550, Nov. 1991.

T. M. Niermann, R. K. Roy, J. H. Patel, and J. A. Abraham, "Test Compaction for Sequential Circuits," IEEE Trans. on CAD, pp. 260-267, Feb. 1992.

T. M. Niermann, W.-T. Cheng, and J. H. Patel, "PROOFS: A Fast Memory Efficient Sequential Circuit Fault Simulator," IEEE Trans. CAD/ICAS, pp 198-207, Feb. 1992.

J. Baxter and J. H. Patel, "Profiling Based Task Migration," Int. Parallel Processing Symp., Beverly Hills, CA, pp. 192-195, Mar. 1992.

E. Rudnick, V. Chickermane, and J. H. Patel, "Probe Point Insertion for AT-Speed Test," 10th IEEE VLSI Test Symp., Atlantic City, NJ., pp. 223-228, Apr. 1992.

S. Kim, P. Banerjee, V. Chickermane, and J. H. Patel, "APT: An Area-Performance-Testability Driven Placement Algorithm," Design Automation Conf., Anaheim, CA, pp. 141-146, June 1992.

J. Lee and J. H. Patel, "Hierarchical Test Generation Under Intensive Global Functional Constraints," Design Automation Conf., Anaheim, CA, pp. 261-266, June1992.

P. Mazumder and J. H. Patel, "An Efficient Design of Embedded Memories and Their Testability Analysis Using Markov Chains," Journal of Electronic Testing: Theory and Applications, vol. 3, pp. 235-250, 1992.

J. Baxter, B. Ramkumar, and J. H. Patel, "Compile Time Parallel Resource Allocation for Unbounded Tree Structured Task Graphs" Int. Conf. on Parallel Processing, vol. I, pp. 202-210, Aug. 1992.

V. Chickermane, J. Lee, and J. H. Patel, "Design for Testability Using Architectural Descriptions," Int. Test Conference, Baltimore, MD, pp. 752-761, Sept. 1992.

E. Rudnick, W. K. Fuchs, and J. H. Patel, "Diagnostic Fault Simulation of Sequential Circuits," Int. Test Conference, Baltimore, MD, pp. 178-185, Sept. 1992.

J. Lee and J. H. Patel, "An Instruction Sequence Assembling Methodology for Testing Microprocessors," Int. Test Conference, Baltimore, MD, pp 49-58, Sept. 1992.

V. Chickermane, J. Lee and J. H. Patel, "A Comparative Study of Design for Testability Methods Using High-Level and Gate-Level Descriptions," Int. Conf. Computer-Aided Design, Santa Clara, CA, pp. 620-624, Nov. 1992.

R. K. Roy, A. Chatterjee, J. H. Patel, J. A. Abraham, and M. A. d'Abreu, "Automatic Test Generation for Linear Digital Systems with Bi-Level Search Using Matrix Transform Methods," Int. Conf. Computer-Aided Design, Santa Clara, CA, pp. 224-228, Nov. 1992.

G. S. Greenstein and J. H. Patel, "E-PROOFS: A CMOS Bridging Fault Simulator," Int. Conf. Computer-Aided Design, Santa Clara, CA, pp. 268-272, Nov. 1992.

J. H. Patel and G. Greenstein, "Accurate CMOS Bridging Fault Simulation," Int. Electron Devices and Materials Symp., Taipei, Taiwan, Nov, pp 170-174, 1992.

J. Fu, J. H. Patel, and B. L. Janssens, "Stride Directed Prefetching in Scalar Processors," Int. Symp. on Micro-Architecture, Portland, OR, Dec. 1992.

J. W-C. Fu, and J. H. Patel, "Trace Driven Simulation Using Sampled Trees," Hawaii Int. Conf. on Systems Sciences, Mauii, Hawaii, pp. 211-220, Jan 1993.

J. Lee, E. M. Rudnick, and J. H. Patel, "Architectural-Level Fault Simulation Using Symbolic Data," European Design Automation Conf., Paris, France, pp. 437-442, Feb 1993.

J. Lee, V. Chickermane, and J. H. Patel, "Impact of High Level Functional Constraints on Testability," VLSI Test Symp., Atlantic City, pp. 309-312, NJ, Apr 1993.

J. Lee and J. H. Patel, "Testability Analysis Based on Structural and Behavioral Information," VLSI Test Symp., Atlantic City, pp. 139-145, NJ, Apr 1993.

V. Chickermane, E. M. Rudnick, P. Banerjee and J. H. Patel, "Non-Scan Design-for-Testability Techniques for Sequential Circuits," Design Automation Conf., Dallas, Tx, pp. 236-241, Jun 1993.

I. Pomeranz, S. M. Reddy, and J. H. Patel, "Theory and Practice of Sequential Machine Testing and Testability," Fault Tolerant Computing Symp., Toulouse, France, pp. 330-337, Jun 1993.

H. Cha, E. M. Rudnick, G. S. Choi, J. H. Patel and R. K. Iyer, "A Fast and Accurate Gate-Level Transient Fault Simulation Environment," Fault Tolerant Computing Symp., Toulouse, France, pp. 330-337, Jun 1993, pp. 310-319.

J. W-C. Fu and J. H. Patel, "Memory Reference Behavior of Compiler Optimized Programs on High Speed Architectures," Int. Conf. Parallel Processing, vol. II, pp. 87-94, Aug 1993.

J. Rearick and J. H. Patel, "Fast and Accurate CMOS Bridging Fault Simulation", Int. Test Conf.

Baltimore, MD, vol. II, pp. 54-61, Oct 1993.

J. Lee and J. H. Patel, "An Architectural Level Test Generator Based on Non-Linear Equation Solving," Journal of Electronic Testing (JETTA), vol. 4, no. 2, pp. 137-150, 1993.

A. N. Choudhary, J. H. Patel, and N. Ahuja, "NETRA: A Hierarchical and Partitionable Architecture for Computer Vision Systems," IEEE Trans. Parallel and Distributed Systems, vol.4, no. 10, pp. 1092-1104, Oct. 1993.

H. Cha and J. H. Patel, "A Logic-Level Model for $alpha$-Particle Hits in CMOS

Circuits," Int. Conf. Comput. Design, Cambridge, MA, pp. 538-542, Oct. 1993.

Pi-Yu Chung, Ibrahim N. Hajj, and Janak H. Patel, ``Efficient Variable Ordering Heuristics for Shared ROBDD,'' Proc. of the Int. Symp. on Circuits and Systems, pp. 1690-1693, 1993.

E. M. Rudnick, J. G. Holm, D. G. Saab, and J. H. Patel, "Application of Simple Genetic Algorithms to Sequential Circuit Test Generation," Euro. Des. & Test Conf., Paris, France, pp. 40-46, Mar. 1994.

J. J. Baxter, J. W. C. Fu, B. Ramkumar and J. H. Patel, "Hybrid Resource

Management Algorithms for Multicomputer Systems," Int. Parallel Processing Symp., Cancun, Mexico, pp. 482-489, Apr. 1994.

E. M. Rudnick, J. H. Patel, G. S. Greenstein, T. N. Niermann, "Sequential Circuit Test Generation in a Genetic Algorithm Framework," 31st Design Automation Conf., June 1994, pp. 698-704.

S. Parkes, P. Banerjee, and J. Patel, "ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation," 31st Design Automation Conf., June 1994, pp. 717-722.

V. Chickermane, J. Lee, and J. H. Patel, "Addressing Design for Testability at the Architectural Level," IEEE Trans. Comput.-Aided Des. of Integrated Circuits and Syst., vol. 13, no. 7, Jul. 1994, pp 920-934.

E. M. Rudnick, V. Chickermane, and J. H. Patel, "An Observability Enhancement Approach for Improved Testability and At-Speed Test," IEEE Trans. Comput.-Aided Des. of Integrated Circuits and Syst., vol. 13, no. 8, pp. 1051-1056, Aug. 1994.

H. Cha and J. H. Patel, "Latch Design for Transient Pulse Tolerance", Int. Conf. Comput. Des., Cambridge, MA, pp. 385-388, Oct. 1994.

Jaushin Lee and Janak H. Patel, "Architectural Level Test Generation for Microprocessors," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 10, Oct 1994, pp. 1288-1300.

A. Dharchoudhury, S. M. Kang, H. Cha and J. H. Patel, "Fast Timing Simulation of Transient Faults in Digital Circuits," Int. Conf. on CAD-94, San Jose, CA, pp. 719-722, Nov. 1994.

Elizabeth M. Rudnick and Janak H. Patel, "A Genetic Approach to Test Application Time Reduction for Full Scan and Partial Scan Circuits," 8th Int. Conf. on VLSI Design, New Delhi, India, pp. 288-293, Jan. 1995.

Jonathan Simonson and Janak H. Patel, "Use of Preferred Preemption Points in Cache-Based Real-Time Systems," Proc. of IEEE IPDS '95, Erlangen, Germany, pp. 316-325., Apr. 24-26 1995.

S. Vankataraman, I. Hartanto, W. K. Fuchs, E. Rudnick, S. Chakravarty, and J. H. Patel, "Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists, 32nd Design Automation Conf., San Francisco, CA, pp. 133-138, June 1995.

E. M. Rudnick and J. H. Patel, "Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation," 32nd Design Automation Conf., San Francisco, CA, pp. 183-188, June 1995.

Paul Thadikaran, Sreejit Chakravarty, and Janak Patel, "Fault Simulation of I _DDQ Tests for Bridging Faults in Sequential Circuits,'' 25th Int. Symp. on Fault Tolerant Computing, Pasadena, CA, pp. 340-349, June 1995.

Michael Hsiao and Janak Patel, "A New Architectural-Level Fault Simulation Using Propagation Prediction of Grouped Fault-Effects,'' Int'l Conf. on Computer Design: VLSI in Computers & Processors, Austin, Texas, pp. 628-635, Oct. 1995.

Eiji Harada and Janak H. Patel, "Overhead Reduction Techniques for Hierarchical Fault Simulation,'' The Fourth Asian Test Symp. , Bangalore, India, pp. 79-85, Nov. 23-24, 1995.

Keerthi Heragu, Janak H. Patel and Vishwani D. Agrawal, "Improving Accuracy in Path Delay Fault Coverage Estimation,'' 9th Int. Conf. on VLSI Design, pp. 422-425, Jan. 1996.

Jaushin Lee, and Janak H. Patel, "Hierarchical Test Generation Under Architectural Level Functional Constraints,'' IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 15, no. 9, Sept. 1996, pp. 1144-1151.

Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, and Janak H. Patel, "Sequential Circuit Testability Enhancement Using a Nonscan Approach,'' IEEE Trans. on the Very Large Scale Integration (VLSI Systems), vol. 3, no. 2, pp. 333-338, June 1995.

Michael S. Hsiao, Elizabeth M. Rudnick and Janak H. Patel,"Alternating Strategies for Sequential Circuit ATPG,'' European Design and Test Conf., Paris, France, Mar. 11-14, pp. 368-374, 1996.

Keerthi Heragu, Janak H. Patel, and Vishwani D. Agrawal, "Segment Delay Faults: A New Fault Model,'' Proc. of 14th IEEE VLSI Test Symp., Princeton, NJ, pp. 32-39, Apr. 28 - May 1, 1996.

Michael S. Hsiao, Elizabeth M. Rudnick and Janak H. Patel, "Automatic Test Generation Using Genetically-Engineered Distinguishing Sequence,'' Proc. of 14th IEEE VLSI Test Symp., Princeton, NJ, pp. 216-223, Apr. 28 - May 1, 1996.

Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, and Janak H. Patel, "Genetic-Algorithm-Based Test Generation for Current Testing of Bridging Faults in CMOS VLSI Circuits,'' Proc. of 14th IEEE VLSI Test Symp., Princeton, NJ, pp. 456-462, Apr. 28 - May 1, 1996.

Dong Xiang, Srikanth Venkataraman, W. Kent Fuchs, and Janak H. Patel, "Partial Scan Design Based on Circuit State Information,'' Proc. 33rd Design Automation Conf., Las Vegas, NV, pp. 807-812, June 3-7, 1996.

Jonathan Simonson and Janak H. Patel, "Performance Analysis Tool for Cache-Based Real-Time Systems with Preemptions,'' Proc. of 2nd Annual IEEE Int. Computer Performance & Dependability Symp., (IPDS), Urbana, IL, pp. 210-218, Sept. 4-6, 1996.

Elizabeth M. Rudnick, Janak H. Patel, and Irith Pomeranz, "On Potential Fault Detection in Sequential Circuits,'' Proc. of Int. Test Conf., Washington DC, pp. 142-149, Oct.20-25, 1996.

Dong Xiang and Janak H. Patel, "A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information,'' Proc. of Int. Test Conf., Washington DC, pp. 548-557, Oct.20-25, 1996.

Tzuhao Chen, Ibrahim N. Hajj. Elizabeth M. Rudnick, Janak H. Patel, "An Efficient IDDQ Test Generation Scheme for Bridging Faults in CMOS Digital Circuits,'' Digest of Papers for 1996 IEEE International Workshop on IDDQ Testing, pp. 74-78, Oct. 24-25, 1996.

Keerthi Heragu, Janak H. Patel, and Vishwani D. Agrawal, "SIGMA: A Simulator for Segment Delay Faults'' Proc. IEEE/ACM Int'l Conf. on Comp. Aided Design, San Jose, CA, pp. 502-508, Nov. 10-14, 1996.

Frank F. Hsu, Elizabeth M. Rudnick, and Janak H. Patel "Enhancing High-Level Control-Flow for Improved Testability,'' Proc. IEEE/ACM Int'l Conf. on Comp. Aided Design, San Jose, CA, pp. 322-328, Nov. 10-14, 1996.

Elizabeth M. Rudnick and Janak H. Patel, "Simulated-Based Techniques for Dynamic Test Sequence Compaction,'' Proc. IEEE/ACM Int'l Conf. on Comp. Aided Design, San Jose, CA, pp. 67-73, Nov. 10-14, 1996.

Frank F. Hsu, Elizabeth M. Rudnick, and Janak H. Patel, "Testability Insertion in Behavioral Descriptions,'' Proc. 9th Int. Symp. on System Synthesis, La Jolla, CA, pp. 139-144, Nov. 1996.

Hungse Cha, Elizabeth M. Rudnick, Janak H. Patel, Ravishankar K. Iyer and Gwan S. Choi, ``A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults,'' IEEE Trans. on Computers, vol 45, no. 11, pp. 1248-1256, Nov. 1996.

Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel and Prithviraj Banerjee, "Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation,'' Proc. of the 10th International Conf. on VLSI Design, Hyderabad, India, pp. 475-481, Jan. 1997.

Elizabeth M. Rudnick and Janak H. Patel, "Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation,'' Proc. of the 10th Int. Conf. on VLSI Design, Hyderabad, India, pp. 495-501, Jan. 1997.

Charles R. Graham, Elizabeth M. Rudnick and Janak H. Patel, "Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits," Proc. of the 10th Int. Conf. on VLSI Design, Hyderabad, India, pp. 542-544, Jan. 1997.

Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel, "Sequential Circuit Test Generation Using Dynamic State Traversal,'' 1997 European Design & Test Conf., Paris, France, pp. 22-28, Mar. 17-20, 1997.

Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel, "Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors,'' Proc. of the IEEE VLSI Test Symp., Monterey, CA, pp. 188-195, Apr. 27 - May 1, 1997.

Ismed Hartanto, Vamsi Boppana, Janak H. Patel, and W. Kent Fuchs, "Diagnostic Test Pattern Generation for Sequential Circuits,'' Proc. of the IEEE VLSI Test Symp., Monterey, CA, pp. 196-202, Apr. 27 - May 1, 1997.

Dilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, and Prithviraj Banerjee, "SPITFIRE: Scalable Parallel Algorithms for Test Set Partitioned Fault Simulation,'' Proc. of the IEEE VLSI Test Symp., Monterey, CA, pp. 274-281, Apr. 27 - May 1, 1997.

Jian-Kun Zhao, Elizabeth M. Rudnick, and Janak H. Patel, "Static Logic Implication with Application to Redundancy Identification,'' Proc. of the IEEE VLSI Test Symp., Monterey, CA, Apr. 27 - May 1, 1997, pp. 288-293.

Gurjeet S. Saund, Michael S. Hsiao, and Janak H. Patel, "Partial Scan Beyond Cycle Cutting,'' Proc. of FTCS, Seattle, WA, pp. 320-328, June 24-27, 1997.

Dilip Krishnaswamy, Prithviraj Banerjee, Elizabeth M. Rudnick, and Janak H. Patel, "Asynchronous Parallel Algorithms for Test Set Partitioned Fault Simulation,'' Proc. of the IEEE 11th Workshop on Parallel and Distributed Simulation (PADS'97), Lockenhaus, Austria, pp. 30-37, June 10-13, 1997.

Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel, "K2: An Estimator for Peak Sustainable Power of VLSI Circuits,'' Proc. of the 1997 Int. Symp. on Low Power Electronics and Design (ISLPED'97), Monterey, CA, pp. 178-183, Aug. 18-20, 1997.

Elizabeth M. Rudnick and Janak H. Patel, "Putting the Squeeze on Test Sequences,'' Proc. of Int. Test Conf., Washington, D.C. , pp. 723-732, Nov. 1-6, 1997.

James P. Cusey and Janak H. Patel, "BART: A Bridging Fault Test Generator for Sequential Circuits,'' Proc. of Int. Test Conf., Washington, D.C., pp. 838-847, Nov. 1-6, 1997.

Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel, "Effects of Delay Models on Peak Power Estimation of VLSI Sequential Circuits,'' Proc. IEEE/ACM Int. Conf. on Comp. Aided Design, San Jose, CA, pp. 45-51, Nov. 9-13, 1997.

Keerthi Heragu, Janak H. Patel, and Vishwani D. Agrawal, "Fast Identification of Untestable Delay Faults Using Implications,'' Proc. IEEE/ACM Int. Conf. on Comp. Aided Design, San Jose, CA, pp. 642-647, Nov. 9-13, 1997.

Keerthi Heragu, Vishwani D. Agrawal, Micahel L. Bushnell, and Janak H. Patel, "Improving a Nonenumerative Method to Estimate Path Delay Fault Coverage,'' IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 7, pp. 759-762, July 1997.

Michael S. Hsiao, Gurjeet S. Saund, Elizabeth M. Rudnick, and Janak H. Patel, "Partial Scan Selection Based on Dynamic Reachability and Observability Information,'' Proc. of the Int. Conf. on VLSI Design, Chennai, India, Jan. 4-7, 1998, pp. 174-180.

Srikanth Venkataraman, W. Kent Fuchs, and Janak H. Patel, "Diagnostic Simulation of Sequential Circuits Using Fault Sampling,'' Proc. of the Int. Conf. on VLSI Design, Chennai, India, Jan. 4-7, 1998, pp. 476-481.

Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein and Thomas M. Niermann, "A Genetic Algorithm Framework for Test Generation,'' IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 9, pp. 1034-1044, Sept. 1997.

Ilker Hamzaoglu and Janak H. Patel, "New Techniques for Deterministic Test Pattern Generation,'' Proc. of the IEEE VLSI Test Symp., Monterey, CA, pp. 446-452, Apr. 26-30, 1998.

Michael S. Hsiao, Elizabeth M. Rudnick and Janak H. Patel, "Application of Genetically Engineered Finite-State-Machine Sequences to Sequential Circuit ATPG,'' IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 3, pp. 239-254, Mar. 1998.

Fulvio Corno, Janak H. Patel, Elizabeth M. Rudnick, Matteo Sonza Reorda, Roberto Vietti, "Enhancing Topological ATPG with High-Level Information and Symbolic Techniques,'' Proc. of Int. Conf. on Circuit Designs, Austin, TX, pp. 504-509, Oct. 5-7, 1998.

Ilker Hamzaoglu and Janak H. Patel, ``Compact Two-Pattern Test Set Generation for Combinational and Full Scan Circuits,'' Proc. of Int. Test Conf., Washington, DC, pp. 944-953, Oct. 18-23, 1998.

Janak H. Patel, "Stuck-at Fault: A Fault Model for the Next Milennium,'' Proc. of Int Test Conf., Washington, DC, p. 1166, Oct. 18-23, 1998,.

Frank F. Hsu and Janak H. Patel, "High-level Variable Selection for Partial-Scan Implementation,'' Proc. of the IEEE/ACM Int. Conf. On Computer Aided Design, San Jose, CA., pp. 79-84, Nov. 8-12, 1998.

Ilker Hamzaoglu and Janak H. Patel, "Test Set Compaction Algorithms for Combinational Circuits,'' Proc. of the IEEE/ACM International Conf. on Computer Aided Design, San Jose, CA., pp. 283-289, Nov. 8-12, 1998.

Janak H. Patel, "Retrospective: Improving the Throughput of a Pipeline by Insertion of Delays,'' 25 Years of the Int. Symp. on Computer Architecture, p. 5, 1998.

Janak H. Patel, `"Retrospective: A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories,'' 25 Years of the Int. Symp. on Computer Architecture, pp. 39-41, 1998.

Keerthi Heragu, Janak H. Patel, and Vishwani E. Agrawal, "A Test Generator for Segment Delay Faults,'' Proc. of 12th Int'l Conf. on VLSI Design, Goa, India, pp. 484-491. Jan. 7-10, 1999.

Michael S. Hsiao, Elizabeth M. Rudnick and Janak H. Patel, "Fast Static Compaction Algorithms for Sequential Circuit Test Vectors,'' IEEE Trans. on Computers, vol. 48, no. 3, pp. 311-322, March 1999.

Elizabeth M. Rudnick and Janak H. Patel, "Efficient Techniques for Dynamic Test Sequence Compaction,'' IEEE Trans. on Computers, vol. 48, no. 3, pp. 323-330, March 1999

Ilker Hamzaoglu and Janak H. Patel, "`Reducing test application time for full scan embedded cores," The Twenty-Ninth Ann. Int'l Symp. on Fault-Tolerant Computing (FTCS), Madison, WI, pp. 260-267, June 15-18, 1999.

Ilker Hamzaoglu and Janak H. Patel, ``New Techniques for Deterministic Test Pattern Generation,'' Journal of Electronic Testing: Theory and Applications, vol. 15, no. 1/2, pp. 63-73, August 1999.

Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, and Janak H. Patel, ``Diagnostic Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists,'' ACM Transactions on Design Automation of Electronic Systems, January 2002, Volume 7, Number 1.

Ilker Hamzaoglu and Janak H. Patel, ``Test Set Compaction Algorithms for Combinational Circuits,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 8, pp. 957-963, August 2000.

Manish Sharma and Janak H. Patel, ``Bounding Circuit Delay by Testing a Very Small Subset of Paths,'' Proceedings of the 18th IEEE VLSI Test Symposium, pp. 333-341, May 2000.

Ilker Hamzaoglu and Janak H. Patel, ``Reducing Test Application Time for Built-in-Self-Test Test Pattern Generator,\ '' Proceedings of the 18th IEEE VLSI Test Symposium, pp. 369-375, May 2000.

Jian-Kun Zhao, Jeffrey A. Newquist and Janak H. Patel, ``A Graph Traversal Based Framework for Sequential Logic Implication with An Application to C-Cycle Redundancy Identification,'' Proceedings of the 14th International Conference on VLSI Design, pp. 163-169, January 2001.