Doctoral Students Supervised or Cosupervised by Professor Janak H. Patel

David Yen (Ph.D. October 1980), Sun Micro, Mountain View, CA, "Performance models for multiprocessor computer systems."

Phil Yeh (Ph.D. December 1980), IBM, Poughkeepsie, NY, "Shared cache organization for multiple-stream computer systems."

Howard Pollard (Ph.D. August 1983), Univ. of New Mexico, Albuquerque, NM, "Fault-tolerant bus communication protocols for computer systems."

Abdallah Saleh (Ph.D. Nov. 1983), Bell Communications Research, Murray Hill, NJ, "Transient error recovery techniques for pipelines and memory systems."

Wu-Tung Cheng (Ph.D. June 1985), Checklogic, San Jose, CA, "Testing and error detection in iterative logic arrays."

Mohammad Malkawi (Ph.D. July 1986), Univ. of Wisconsin, Milwaukee, WI, "Compiler directed memory management for numerical programs."

Pinaki Mazumder (Ph.D. Sept. 1987), Univ. of Michigan, Ann Arbor, MI, "Testing and fault-tolerance aspects of high density VLSI memory."

Subhasis Laha (Ph.D. Nov. 1987), AT&T, Naperville, IL, "Accurate low-cost methods for performance evaluation of cache memory systems."

Richard J. Eickemeyer (Ph.D. Dec. 1987), IBM, Endicott, NY, "Performance evaluation of multiple register-set architectures and cache memories."

Susheel Chandra (Ph.D. 1989), Sony Microsystems, San Jose, CA, "Techniques to speedup test generation for VLSI circuits."

Alok Choudhary (Ph.D. 1989), Syracuse Univ., Syracuse, NY, "Parallel architectures and parallel algorithms for integrated vision systems."

Thomas Niermann (Ph.D. March 1991), Sunrise Test, Sunnyvale, CA, "Techniques for sequential circuit automatic test generation."

Robert Horst (Ph.D. May 1991), Tandem Computers, Cupertino, CA, "Task flow: A novel approach to fine-grain wafer-scale parallel computing."

Rabindra Roy (Ph.D. January 1992), NEC Research, Princeton, NJ, "Automatic test generation for bit-serial VLSI digital signal processors."

John Fu (Ph. D. May 1992), Intel, Folsom, CA, "Performance evaluation of memory systems for high speed computers."

Jeff Baxter (Ph. D. August 1992), Intel, Santa Clara, CA, "Resource management for distributed memory multicomputers."

Jaushin Lee (Ph. D. September 1992), Univ. of Ill, Urbana, IL, "Architectural level test generation and fault-simulation."

Vivek Chickermane (Ph. D. May 1993), IBM, Endicott, NY, "Design and synthesis for testability using architectural descriptions."

Elizabeth Rudnick (Ph.D. August 1994), Motorola, Austin, TX, "Simulation-based techniques for sequential circuit testing."

Hungse Cha (Ph.D. August 1994), HP, Cupertino, CA, "A gate level simulator for alpha-particle-induced transient faults."

Jonathan Simonson (Ph.D. August 1996), Univ. of Arkansas, Fayetteville, AR, "Cache memory management in real-time systems."

Michael Hsiao (Ph.D. June 1996), Rutgers Univ., Piscataway, NJ, "Sequential circuit test generation using genetic techniques."

Keerthinarayan Heragu (Ph.D. November 1997), Texas Instruments, Dallas, TX, "New techniques to verify timing correctness of integrated circuits."

Frank Hsu (Ph.D. August 1998), Texas Instruments, Dallas, TX, "High-level testability analysis and enhancement for digital systems."

Ilker Hamzaoglu (Ph.D. September 1999), Motorola Inc, Schaumburg, IL, " Test Pattern Generation and Test Application Time Reduction Algorithms for VLSI Circuits"

Manish Sharma

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Masters Students Supervised or Cosupervised by Professor Janak H. Patel

Elmer Pflug (M.S. May 1980), Fairchild Corp., Maine, "Realizing a large memory space on a microprocessor system."

Greg Grohoski (M.S. June 1981), IBM, Yorktown Heights, NY, "An instruction prefetch model for pipelined execution units."

Andy Kessler (M.S. September 1981), Custom Integration, Clark, NJ, "Reconfigurable parallel pipelines for fault-tolerance."

Leona Fung (M.S. December 1981), LSI Logic, Milpitas, CA, "Concurrent error detection in arithmetic and logic units."

Craig Ufferheide (M.S. January 1982), US Air Force, San-Diego, CA, "Performance analysis of reconfigurable computer systems subject to intermittent faults."

Sheri Abrams (M.S. August 1982), Hewlett Packard, Cupertino, CA "Some effects of a deviation in threshold voltage on the operation of MOS VLSI circuits."

Mike Chin (M.S. September 1982), Tandem Computers, Cupertino, CA, "The design of a VLSI systolic array cell with concurrent error detection."

John Theodosiou (M.S. August 1983), Univ. of IL, Urbana, IL, "Design, performance and fault-tolerance of interconnection networks."

Frank Massa (M.S. December 1983), Bell Laboratories, Indian Hill, IL, "The design of a concurrent error detecting complex multiplier for VLSI."

Subhasis Laha (M.S. March 1984), Univ. of IL, Urbana, IL, "Design of fault-tolerant adders and multipliers using time redundancy."

Mark Papamarcos (M.S. May 1984), ESL (TRW subsidiary), Sunnyvale, CA, "A low-overhead coherence solution for bus-organized multiprocessors with private cache memories."

Paul Mui (M.S. July 1984), Bell Laboratories, Indian Hill, IL "Design of a bit-sliced processor array with built-in-self-test."

Daniel Colglazier (M.S. August 1984), IBM, Poughkeepsie, NY, "A performance analysis of multiprocessors using two-level caches."

Andrew Read (M.S. January 1985), ESL (TRW subsidiary), Sunnyvale, CA, "A micro program assembler."

Charles Stancil (M.S. May 1985), IBM, Boca Raton, FL, "Algorithms for minimizing test sets for CMOS VLSI circuits."

Sanjaykumar T. Patel (M.S. August 1985), IBM, Poughkeepsie, NY, "Development of an automatic test pattern generation package."

Richard J. Eickemeyer (M.S. August 1985), Univ. of IL, Urbana, IL, "A parallel stack processor to reduce procedure-call overhead."

Susheel Chandra (M.S. December 1985), Univ. of IL, Urbana, IL, "Dynamic fault collapsing in fault simulation."

Brian Kleven (M.S. May 1986) "A special-purpose computer architecture for fault simulation."

Mary Henske (M.S. December 1986), "TGIFS: A test generation and fault simulation package."

Jeff Baxter (M.S. December 1986), Univ. of IL, Urbana, IL, "A multiprocessor fault simulation architecture."

Mike Kim (M.S. September 1987), AT&T, Naperville, IL "A logic animation package for a computer aided engineering workstation."

Robert Swanson (M.S. December 1987), IBM-FSD, Mannasas, VA, "Development of a test generation and fault simulation package for VLSI circuits."

Tom Niermann (M.S. December 1988), Univ. of Illinois, Urbana, IL, "Concurrent automatic test generation for delay faults."

Utpal Dave (M.S. August 1989), "High-level methodologies for test generation and logic simulation."

Vivek Chickermane (M.S. August 1990), IBM Corp., Endicott, NY, "An optimization, based methodology of partial scan design."

Jonathan Simonson (M.S. August 1991), Univ. of IL, Urbana, IL, "A programmable crossbar switch for multiprocessor systems."

Wendy Thirtle (M.S. March 1992), IBM Federal Systems Division, Manassas, VA, "A parallel-implementation of test detect."

Scott Heydinger (M.S. December 1992), "Fault ordering in sequential automatic test pattern generation."

Jeff Rearick (M.S. January 1993), Hewlett Packard, Fort Collins, CO, "Fast and accurate CMOS bridging fault simulation."

Michael Hsiao (M.S. May 1993), Univ. of IL, Urbana, IL, "Variable-delay event-driven logic and fault simulation."

James Cusey (M.S. June 1993), Dallas Semiconductor, Dallas TX. "A bridging-fault automatic resistance-based test generator."

Mark Skarpness (M.S. July 1993), Intel Corp., Santa Clara, CA, "Compiled event-driven behavioral VHDL simulator."

Fred Gruner (M.S. October 1994), Intel Corp., Santa Clara, CA, "L-proofs: A leakage fault simulator for CMOS circuits."

Mark Johnson (M.S. August 1994), VLSI Technology Inc., HoffmanEstates, IL, "High level test generation using software testing metrics."

Frank Hsu (M.S. July 1995), Univ. of IL, Urbana, IL, "A novel approach to improve testability of finite state machines."

Pauline Marie Bolte, (M.S. Sept. 1997), "Crosstalk simulation in digital sequential circuits."

Jeffrey Aaron Newquist, (M.S. May 1997), Silicon Graphics, Inc., Mountain View, CA, "Fast logic implication discovery."

Gurjeet Singh Saund, (M.S. May 1997), Chromatic Research, Sunnyvale, CA, "Partial scan beyond cycle-cutting."

Jian-Kun Zhao, (M.S. March 1998), CAE Plus, Inc., Austin, TX, "Static logic implication with application to untestable fault identification."

Manish Sharma, Univ. of Illinois, Urbana, IL (M.S. June 2000), "Delay Fault Testing for Enhanced Full Scan Based Circuits."

Karen E. Wells, (M.S. May 2001), "A Portable Software Tool for Measurement of Transient Errors in Commercial Microprocessors."

Hari Kommaraju

Amit Pandey

Vikram Rao