This paper presents a testable design of DRAM architecture which allows one to access multiple cells in a word line simultaneously. The technique utilizes the two-dimensional organization of the DRAM and the resulting speed up of the conventional algorithms is considerable. This paper specifically investigates the failure mechanisms in the DRAM with trench-type capacitor. As opposed to the earlier approaches for testing parametric faults that employed sliding diagonal type tests with O(n sup {3/2}) complexity, the algorithms discussed in this paper are different and have O(sqrt n) complexity. These algorithms can be applied externally from the chip and also they can be easily generated for Built-In Self-Test (BIST) applications.