This paper presents a design strategy for efficient and comprehensive parallel testing of both Random-Access Memory (RAM) and Content-Addressable Memory (CAM). Based on this design-for-testability approach, parallel testing algorithms for CAM's and RAM's are developed for a broad class of pattern-sensitive faults. The resulting test procedures are significantly more efficient than previous approaches. For example, the design-for-testability strategy allows an entire w-word CAM to be read in just one operation with a resulting speedup in testing as high as w. In the case of an n-bit RAM, the improvement in test efficiency is by a factor of O(sqrt n). The overall reduction in testing time is considerable for large size memories.