This paper addresses the problem of bridging fault simulation under the conventional voltage testing environment. A new method is proposed to provide electrical-level simulation accuracy for bridging fault simulation, without paying the performance penalties associated with electrical-level simulation. A three-level simulation model is used, balancing the tradeoffs among gate-level, switch-level, and electrical-level simulation. Large memory overheads are avoided by localizing the fault, and by only performing electrical-level simulation in the area around the fault. This approach is sufficiently flexible to model feedback faults, BiCMOS circuits, stuck-open faults, and any fault that can be described with a circuit netlist. Tests were run on several ISCAS combinational and sequential benchmark circuits, using realistic cells and transistor parameters; results show that accurate simulations can be performed in reasonable time. An added observation was the need for two-threshold testing at output pins, to ensure detection of bridging faults that cause indeterminate logic values that propagate to the circuit's primary outputs.