This paper proposes a novel strategy for a single error correction and double error detection (SEC-DED) in a multi-level memory system. Parallel Signature Analyzer (PSA) is usually integrated in the DRAM to reduce the testing cost and augment the memory testability. The proposed scheme utilizes the presence of PSA for on-line fault detection and thereby needs minimal extra overhead within the chip. For a 2-level w word memory system, the proposed technique needs pnly one additional chip as opposed to ( log sub 2 w + 2) in the Hamming code. The on-chip error correcting technique has been shown to improve the overall reliability of the memory system and reduce the alpha-particle induced soft error rate by a factor of 10 sup 6. The main contribution of this work is to integrate the concept of testability and reliability for the future generation gargantuan semiconductor RAM chips.
This research was partly supported by the SRC under the grant number 86-12-109.