This paper proposes a new test algorithm for pattern-sensitive faults in large size RAM with high circuit density. The algorithm tests an n-bit RAM in 195 sqrt n time to detect both static and dynamic pattern-sensitive faults over the 9-neighborhood of every memory cell. A 4M bit RAM can be tested by the proposed algorithm several thousand times faster than the conventional sequential algorithms for detecting pattern-sensitive faults. The test speed up has been achieved by writing a test data simultaneously over many cells, and the stored data are tested simultaneously by a parallel comparator and error detector in read operation. The existing RAM architecture has been modified very little so that the proposed technique can be implemented very easily even in switched capacitor DRAM with low inter celler pitch width. The proposed test procedure has also been applied to built-in self testing and compared with other BIST implementations.
This research was partly supported by the Semiconductor Research Corporation under the contract number 86-12-109.
RAM, Static Pattern Sensitive Fault, Dynamic Pattern Sensitive Fault, Built-In Self Test