An efficient strategy to utilize Parallel Signature Analyzer (PSA) for concurrent soft-error correction in DRAM's is described. For a two-level w-word memory system, the proposed technique needs only one additional chip as opposed to ( log sub 2 w + 2) in the conventional Hamming code. Such an error-correction circuit (ECC) significantly improves the reliability of the memory system.
This research was partly supported by the NSF Research Initiation Awards under the grant number MIPS 8808978, by the SRC under the grant number 86-12-109, by the ONR under the grant number N00014-85-K-531, by the Bell Northern Research Laboratory, by the Digital Equipment Corporation, and partly by the URI-Army under the grant number DAAL-03-87-K007.