Some recent studies show that an at-speed sequential or functional test is better than a test executed at lower speed. Design-for-testability approaches based on full scan, partial scan, or silicon-based solutions such as Crosscheck achieve very high stuck-at fault coverage. However, in all these cases, the tests have to be applied at speeds lower than the operation speed of the circuit. In this paper, a design-for-test method which permits at-speed testing is introduced. The method is based on probe point insertion for improved observability, and it requires enhancements to an existing sequential circuit fault simulator. Faults which can be activated but not detected at existing primary outputs are targeted. A minimal set of probe points is selected to detect these faults, and the probe points are compressed to one or two output pins using exclusive-OR trees. The issue of aliasing of fault effects is addressed. Improvements in fault coverage were made for all 17 of the ISCAS89 sequential benchmark circuits studied. Fault coverages between 99% and 100% were obtained for seven circuits, and 100% ATG effectiveness achieved on all but two circuits.