This paper presents a new design strategy for efficient and comprehensive parallel testing of high-density, MOS Random-Access Memories (RAM's). Based on this design-for-testability approach, parallel-test algorithms for RAM's are developed for a broad class of pattern-sensitive faults. Specifically, the paper discusses two algorithms which are significantly more efficient than previous approaches. The first algorithm detects the static and dynamic pattern-sensitive faults over a neighborhood of five cells. The second algorithm tests the symmetric pattern-sensitive faults over a neighborhood of nine cells. It tests an n-bit RAM organized as a sqrt n times sqrt n array in 97 sqrt n memory cycles. The design-for-testability approach modifies the existing RAM architecture very little so that the proposed technique can be implemented very easily. The additional overhead is only about 2 sqrt n transistors. The low overhead allows high reliability and the additional circuit for each bit line can fit within the 3 lambda to 6 lambda pitch width in high-density, single-transistor Dynamic RAM. Even though the proposed test algorithm is designed to detect the pattern-sensitive faults, the modified architecture can be readily used to speed up other conventional algorithms of linear complexity by a factor of O(sqrt n).
This research was supported by the Semiconductor Research Corporation (SRC) under the contract 86-12-109, by the University Research Initiation program of US Army under the contract number DAAL-03-87-K-0007, and by the Research Initiation program of the National Science Foundation under the grant number MIP-8808978.
RAM, Memory Testing, Static Pattern-Sensitive Fault, Dynamic Pattern-Sensitive Fault.