Modern circuit design methods are moving away from schematic-based design to Hardware Description Languages (HDLs). In a language based design methodology, a high level description is created, the design is verified, and then the logic is created or synthesized. The high level behavioral description represents a new source of information about the circuit which may be useful in test generation. This thesis explores that possibility. This thesis borrows techniques used in software testing [1, 2, 3, 4, 5, 6] for high level test generation. Systems have been built for programming languages, such as C and Fortran, that will give structural coverages of software programs [7, 8], and that will automatically generate data to obtain such coverages [9, 10, 11]. Since an HDL high level description is basically a software program, these techniques could also be applied to an HDL description. The experiment presented generates a test suite that will satisfy a particular software structural testing criteria for the behavioral VHDL (Very High Speed Integrated Circuit HDL)  description and then uses PROOFS  to evaluate these vectors on the functionally equivalent logic level description. PROOFS grades the circuit on the number of stuck-at-faults detected. This fault coverage is then compared to test vectors generated by HITEC , a deterministic gate level test generator. In this way, we can see the correlation of tests generated from the gate level description and tests generated from the behavioral description of a circuit. This thesis is divided into six chapters. Chapter 2 presents an introduction to VHDL. Chapter 3 is a short discussion on software testing techniques. Chapter 4 provides the research and results. Chapter 5 is a discussion on the results. Chapter 6 gives concluding remarks.