BITG_DLX: A Biased Random Instruction Generator for the DLX Processor
BITG_DLX, or BITG
is a biased random instruction generator, which forms part of a simulation-based
design verification environment for the DLX benchmark architecture. BITG
generates assembly language programs based on biases specified by the user.
Version 1.0 is currently being distributed to SRC companies and non-profit
educational institutions only. (Others please contact Prof.
Elizabeth M. Rudnick for access.) The program was designed to run under
the Unix environment and has been compiled for both HP and SUN workstations.
It is available to the public on an internal-use-only basis.
The development of these tools was supported by the Semiconductor Research
Corporation and Motorola.
Copyright © 1999 by the University of Illinois. All rights reserved.
Last Updated: August 28, 2000
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