IGATE Fault Simulation

Key Contributors

• Janak Patel
• Hungse Cha
• Eiji Harada
• Michael Hsiao
• Jaushin Lee
• Thomas Niermann
• Elizabeth M. Rudnick

Research Papers

A listing of all published IGATE research papers on fault simulation is included below.

Asynchronous parallel algorithms for test set partitioned parallel fault simulation,
Dilip Krishnaswamy, Prithviraj Banerjee, Elizabeth M. Rudnick, and Janak H. Patel,
Proceedings of the Workshop on Parallel and Distributed Simulation, June 1997.

SPITFIRE: Scalable parallel algorithms for test set partitioned fault simulation,
Dilip Krishnaswamy, Elizabeth M. Rudnick, Prithviraj Banerjee, and Janak H. Patel,
Proceedings of the VLSI Test Symposium, pp. 274-281, April 1997.

Overcoming the serial logic simulation bottleneck in parallel fault simulation,
Elizabeth M. Rudnick and Janak H. Patel,
Proceedings of the International Conference on VLSI Design, pp. 542-544, January 1997.

Dynamic fault grouping for PROOFS: A win for large sequential circuits,
Charles R. Graham, Elizabeth M. Rudnick, and Janak H. Patel,
Proceedings of the International Conference on VLSI Design, pp. 495-501, January 1997.

On potential fault detection in sequential circuits,
Elizabeth M. Rudnick, Janak H. Patel, and Irith Pomeranz
Proceedings of the International Test Conference, pp. 142-149, October 1996.

Overhead reduction techniques for hierarchical fault simulation,
Eiji Harada and Janak H. Patel,
Proceedings of the Fourth Asian Test Symposium, 1995.
Abstract

A new architectural-level fault simulation using propagation prediction of grouped fault-effects,
Michael S. Hsiao and Janak H. Patel,
Proceedings of the IEEE International Conference on Computer Design,
October 1995.

A parallel algorithm for fault simulation based on PROOFS,
Steven Parkes, Prithviraj Banerjee, and Janak H. Patel,
Proceedings of the IEEE International Conference on Computer Design,
pp. 616-621, October 1995.
Abstract

Fast timing simulation of transient faults in digital circuits,
Abhijit Dharchoudhury, Sung Mo Kang, Hungse Cha, and Janak H. Patel,
Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 719-722, November 1994.

Latch design for transient pulse tolerance,
Hungse Cha and Janak H. Patel,
Proceedings of the International Conference on Computer Design,
pp. 385-388, October 1994.

A gate level simulator for alpha-particle-induced transient faults,
Hungse Cha,
Ph.D. dissertation, Department of Electrical and Computer Engineering, Technical Report CRHC-94-13/UILU-ENG-94-2228,
University of Illinois, August 1994.

A logic-level model for alpha-particle hits on CMOS circuits,
Hungse Cha and Janak H. Patel,
Proceedings of the International Conference on Computer Design,
pp. 538-542, October 1993.

A fast and accurate gate-level transient fault simulation environment,
Hungse Cha, Elizabeth M. Rudnick, Gwan S. Choi, Janak H. Patel, and Ravishankar K. Iyer,
Proceedings of the International Symposium on Fault-Tolerant Computing, pp. 310-319, June 1993.

Variable-delay event-driven logic and fault simulation,
Michael S. Hsiao,
M.S. thesis, Department of Electrical and Computer Engineering,
Technical Report CRHC-93-14/UILU-ENG-93-2226,
University of Illinois, June 1993.

Architectural-level fault simulation using symbolic data,
Jaushin Lee, Elizabeth M. Rudnick, and Janak H. Patel,
Proceedings of the European Conference on Design Automation,
pp. 437-442, February 1993.

Architectural level test generation and fault simulation,
Jaushin Lee,
Ph.D. dissertation, Department of Electrical and Computer Engineering,
Technical Report CRHC-92-20, University of Illinois, August 1992.

PROOFS: A fast, memory-efficient sequential circuit fault simulator,
Thomas M. Niermann, Wu-Tung Cheng, and Janak H. Patel,
IEEE Transactions on Computer-Aided Design of Circuits & Systems,
vol. 11, no. 2, pp. 198-207, February 1992.
Abstract

Methods for reducing events in sequential circuit fault simulation,
Elizabeth M. Rudnick, Thomas M. Niermann, and Janak H. Patel,
Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 546-549, November 1991.

Techniques for sequential circuit automatic test generation,
Thomas M. Niermann,
Ph.D. dissertation, Department of Electrical and Computer Engineering,
Technical Report CRHC-91-8/UILU-ENG-91-2214,
University of Illinois, March 1991.

PROOFS: A fast, memory efficient sequential circuit fault simulator,
Thomas M. Niermann, Wu-Tung Cheng, and Janak H. Patel,
Proceedings of the ACM/IEEE Design Automation Conference,
pp. 535-540, June 1990.
Abstract

PROOFS: A super fast fault simulator for sequential circuits,
Wu-Tung Cheng and Janak H. Patel,
Proceedings of the IEEE European Conference on Design Automation,
pp. 475-479, March 1990.

Accurate logic simulation in the presence of unknowns,
Susheel J. Chandra and Janak H. Patel,
Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 34-37, November 1989.

Dynamic fault collapsing in fault simulation,
Susheel J. Chandra, M.S. thesis, Department of Electrical Engineering,
Technical Report CSG-57/UILU-ENG-86-2235,
University of Illinois, 1986.