IGATE GA-Based Test Generation

Key Contributors

• Janak Patel
• Michael Hsiao
• Elizabeth Rudnick

Research Papers

A listing of all published IGATE research papers on test generation is included below.

Fast sequential circuit test generation using high-level and gate-level techniques
Elizabeth M. Rudnick
Proceedings of the Design, Automation and Test in Europe Conference (DATE), pp. 570-576, February 1998.

Putting the squeeze on test sequences
Elizabeth M. Rudnick and Janak H. Patel,
Proceedings of the International Test Conference, pp. 723-732, November 1997.

Sequential circuit test generation using dynamic state traversal,
Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel,
Proceedings of the European Design and Test Conference, pp. 22-28, March 1997.

Parallel genetic algorithms for simulation-based sequential circuit test generation,
Dilip Krishnaswamy, Michael S. Hsiao, V. Saxena, Elizabeth M. Rudnick, Janak H. Patel, and Prithviraj Banerjee,
Proceedings of the International Conference on VLSI Design, pp. 475-481, January 1997.

Simulation-based techniques for dynamic test sequence compaction
Elizabeth M. Rudnick and Janak H. Patel,
Proceedings of the International Conference on Computer-Aided Design, pp. 67-73, November 1996.

Automatic test generation using genetically engineered distinguishing sequences,
Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel,
Proceedings of the VLSI Test Symposium, pp. 216-223, April 1996.

Alternating strategies for sequential circuit ATPG,
Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel,
Proceedings of the European Design and Test Conference, pp. 368-374, March 1996.

State justification using genetic algorithms in sequential circuit test generation,
Elizabeth M. Rudnick and Janak H. Patel,
Coordinated Science Laboratory, University of Illinois, Urbana, IL,
Technical Report CRHC-96-01/UILU-ENG-96-2201,
January 1996.

Combining deterministic and genetic approaches for sequential circuit test generation
Elizabeth M. Rudnick and Janak H. Patel,
Proceedings of the ACM/IEEE Design Automation Conference, pp. 183-188, June 1995.

A genetic approach to test application time reduction for full scan and partial scan circuits,
Elizabeth M. Rudnick and Janak H. Patel,
Proceedings of the Eighth International Conference on VLSI Design, pp. 288-293, January 1995.

Simulation-based techniques for sequential circuit testing,
Elizabeth M. Rudnick,
Ph.D. dissertation, Department of Electrical and Computer Engineering, Technical Report CRHC-94-14/UILU-ENG-94-2229,
University of Illinois, August 1994.

Sequential circuit test generation in a genetic algorithm framework,
Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, and Thomas M. Niermann,
Proceedings of the ACM/IEEE Design Automation Conference, pp. 698-704, June 1994.

Application of simple genetic algorithms to sequential circuit test generation,
Elizabeth M. Rudnick, John G. Holm, Daniel G. Saab, and Janak H. Patel,
Proceedings of the European Design and Test Conference, pp. 40-45, February 1994.