HITEC/PROOFS: A Sequential Circuit Test Generation and Fault Simulation Package

HITEC/PROOFS is a gate-level, sequential circuit test generation and fault simulation package. Version 1.2 is currently being distributed to non-profit educational institutions only. (Others please contact Prof. Janak Patel for access.) The programs were designed to run under the Unix environment and have been compiled for both HP and SUN workstations. They are available to the public on an internal-use-only basis. The programs target single stuck-at faults in synchronous sequential circuits described in the ISCAS89 benchmark format. Fault lists are automatically generated for all single stuck-at faults in a circuit, and equivalence fault collapsing is performed using structural equivalence. Individual faults are targeted by HITEC, and several passes through the fault list are made, with increasing time and backtrack limits in each successive pass. When a test sequence is successfully generated to detect a target fault, HITEC invokes the PROOFS fault simulator to find all additional faults incidentally detected by the test sequence. Detected faults are then removed from the fault list. After each pass through the fault list, the user is prompted about whether to continue with the next pass; execution terminates when the user responds negatively. PROOFS can also be run separately using a test set supplied by the user.

Access HITEC/PROOFS Software

User Instructions

HITEC/PROOFS User's Manual


The development of these tools was supported in part by the University of Illinois and the Semiconductor Research Corporation.

Copyright © 1995 by the University of Illinois. All rights reserved.

Last Updated: September 10, 1997
Send any questions to liz@uiuc.edu
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