OPUS User Instructions

• opus - program to select flip-flops for partial scan based on cycle breaking and testability measures. Inputs circuit described in *.lev levelized file format (generated by the HITEC preprocessing program, level); makes *.scan file with a list of node identifiers for flip-flops selected. Options are available to break all cycles or to select a given number of flip-flops using cycle breaking and testability measures. The selection based on the Testability measure can pick Flip-Flops after calculating gains for each or calculation of gains several times using a greedy iterative algorithm for selection. The iterative selection procedure can be expensive for large circuits, but testablity gains observed are greater for the same number of flip-flops selected versus a one time calculation of gains.

  opus [options] [selection] (circuit)

  options

  -c : Cuts all cycles in the circuit (default option).

  -f : Fault oriented, selects upto only 10% FF's.

  -p : Limits scan to number of Primary Inputs.

  -n (number) : Selects upto (number) flip-flops after cutting all cycles.

  -t (number) : Selects upto (number) flip-flops only based on Testability measures.

  selection : used only with -n, -t options.

  -i : Testability based selection is performed iteratively.

  -f : Testability based selection is performed only once. (default selection)

• fullscan - program to convert all flip-flops in the *.bench file to primary inputs and primary outputs for test generation purposes. Modified circuit description is placed in *f.bench file, and list of flip-flops is placed in *f.ff file.

  fullscan (circuit)

• makescan - program to convert specified flip-flops in the *.bench file to primary inputs and primary outputs for test generation purposes. Flip-flops to be converted are listed in a *.scan file using node identifiers for the levelized circuit. Modified circuit description is placed in a *s.bench file; *.name file translating gate numbers to names is required as an input file (generated by the HITEC preprocessing program, level). Note that flip-flops listed in the *.scan file must be in the same order as in the levelized circuit (*.lev).

  makescan (circuit)

• num2name - program to convert identifiers of a list of flip-flops to the original symbolic names. Inputs *.scan file with flip-flop identifiers and *.name file translating gate numbers to names (generated by the HITEC preprocessing program, level). Outputs symbolic names of flip-flops in *.scanff file.

  num2name (circuit)

• num2sym - program to convert numeric list of aborted faults to symbolic form. Inputs circuit described in *.lev levelized file format and *.name file translating gate numbers to names (generated by the HITEC preprocessing program, level) and also a list of aborted faults in the *.abt file (generated by HITEC). Outputs symbolic list of faults in *.symflt file.

  num2sym (circuit)

• sym2num - program to convert symbolic list of aborted faults to numeric form. Inputs circuit described in *.lev levelized file format and *.name file translating gate numbers to names (generated by the HITEC preprocessing program, level) and also a symbolic list of faults in the *.symflt file. Outputs numeric list of faults in *.abt file. This program is intended to be used for converting a list of aborted faults to the correct format for use in a modified version of the circuit with design-for-testability logic added.

  sym2num (circuit)

• addmux - program to modify a *.bench file with design-for-testability (DFT) logic. Also inputs a *.scan file with identifiers of flip-flop at which the DFT hardware is inserted and a *.name file translating gate numbers to names (generated by the HITEC preprocessing program, level). Outputs a modified circuit description with DFT hardware which depends on the option selected:

  addmux [-norm] [-hold] [-group] [-group2] [-group3] [-chain2] [-chain3] [-scan] [-load] (circuit)

  norm: Add multiplexors to selected flip-flops so that flip-flops are loaded directly from the primary inputs when the test line is asserted. Number of flip-flops should be less than or equal to number of primary inputs.

  hold: Same as norm option, but place unselected flip-flops in hold mode while selected flip-flops are loaded from primary inputs.

  group: Same as norm option, but 3 flip-flops are connected to each primary input, with only one of the 3 to be loaded at a given time.

  group2: Same as norm option, but 2 flip-flops are connected to each primary input, and both of the flip-flops are loaded at the same time.

  group3: Same as norm option, but 3 flip-flops are connected to each primary input, and all of the flip-flops are loaded at the same time.

  chain2: Same as norm option, but 2 flip-flops are connected from each primary input in a small scan chain.

  chain3: Same as norm option, but 3 flip-flops are connected from each primary input in a small scan chain.

  scan: Add multiplexors to selected flip-flops so that flip-flops are placed in a single scan chain.

  load: Add multiplexors to selected flip-flops so that flip-flops are loaded directly from new primary inputs when the test line is asserted, and flip-flop values are unloaded to new primary outputs when the test line is asserted. This option allows for the emulation of scan testing with a single cycle to scan in and scan out flip-flop values.

An example circuit description is shown below (ISCAS89 s27 circuit):

# 4 inputs

# 1 outputs

# 3 D-type flipflops

# 2 inverters

# 8 gates (1 ANDs + 1 NANDs + 2 ORs + 4 NORs)

INPUT(G0)

INPUT(G1)

INPUT(G2)

INPUT(G3)

OUTPUT(G17)

G5 = DFF(G10)

G6 = DFF(G11)

G7 = DFF(G13)

G14 = NOT(G0)

G17 = NOT(G11)

G8 = AND(G14, G6)

G15 = OR(G12, G8)

G16 = OR(G3, G8)

G9 = NAND(G16, G15)

G10 = NOR(G14, G11)

G11 = NOR(G5, G9)

G12 = NOR(G1, G7)

G13 = NOR(G2, G12)

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