Synthesized Circuits

The synthesized circuits have been used as benchmarks for the Illinois research in VLSI Circuit Testing and were first described in the following paper:

A comparative study of design for testability methods using high-level and gate-level descriptions,
Vivek Chickermane, Jaushin Lee, and Janak H. Patel,
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design,
pp. 620-624, November 1992.

The gate-level circuits were synthesized from high-level descriptions written in the VHSIC Hardware Description Language (VHDL). Characteristics of the circuits are summarized below, including structural sequential depth, number of flip-flops, number of primary inputs, number of primary outputs, total number of collapsed faults, and circuit function.

Circuit Seq. Depth FF'sPI's PO'sFaults Function
am2910 4 87 20 16 2391 12-bit microprogram sequencer
mult16 9 55 18 33 1708 16-bit 2's-complement shift-and-add multiplier
div16 19 50 33 34 2147 16-bit divider using repeated subtractions
pcont2 3 24 9 8 11,300 8-bit controller for DSP applications
piir8o 5 56 9 8 19,920 8-bit digital filter (optimized)
piir8 5 56 9 8 29,689 8-bit digital filter

am2910 is a 12-bit microprogram sequencer which has a stack of depth 5, a stack pointer, a microprogram counter, and a register counter (down counter). A 4-to-1 multiplexer selects the next microprogram address from either the input data bus, the stack, the register counter, or the microprogram counter. The circuit accepts 16 instructions to decide the next microprogram address. More detailed information is available in the AMD Data Book:

The AM2910, a complete 12-bit microprogram sequence controller,
in AMD Data Book, Advanced Micro Devices Inc., Sunnyvale, CA, 1978.

mult16 is a 16-bit 2's complement multiplier which uses a shift-and-add algorithm. The control unit has been implemented using 3-bit and 4-bit counters. There is one start instruction.

div16 is a 16-bit divider that uses repeated subtraction to perform division. A zero-detect unit checks for the divide-overflow condition and flags the termination of the repeated subtraction loop. There is one control instruction: Start.

pcont2 is an 8-bit parallel controller used in DSP applications. This circuit is composed of 8 adders, 2 fixed-point multipliers, and 3 muxes -- all combinational logic. Three registers serve as delay elements. A global reset line resets all the registers, and new data is input every clock cycle. There is no control unit.

piir8 is an 8-point infinite impulse response filter for DSP applications. It has a very regular structure with 7 adders, 8 fixed-point multipliers, 7 8-bit registers, and 7 2-to-1 muxes. The data input and output buses are 8 bits wide. There is no control unit. A global reset line is the only control signal.

piir8o is an optimized verion of piir8.

The synthesized circuits are accessible below in ISCAS89 benchmark format:


Last Updated: January 16, 1997
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