IGATE Test Generation

Key Contributors

• Janak Patel
• Elizabeth Rudnick
• Ilker Hamzaoglu
• Michael Hsiao
• Jaushin Lee
• Thomas Niermann

Research Papers

A listing of all published IGATE research papers on test generation is included below.

Sequential ATPG using combinational algorithms,
Miron Abramovici, Xiaoming Yu, and Elizabeth M. Rudnick,
Proceedings of the Latin Test Workshop, Feburary 2001.

Diagnostic test generation for sequential circuits,
Xiaoming Yu, Jue Wu, and Elizabeth M. Rudnick,
Proceedings of the International Test Conference, Octobor 2000.

Compact test generation using a frozen clock testing strategy,
Elizabeth M. Rudnick and Miron Abramovici,
Journal of Information Science and Engineering, 2000.

Dynamic state traversal for sequential circuit test generation,
Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel,
ACM Transactions on Design Automation of Electronic Systems, vol. 5, no. 3, pp. 548-565, July 2000.

Combining symbolic and genetic techniques for efficient sequential circuit test generation,
M. Boschini, Xiaoming Yu, Franco Fummi, and Elizabeth M. Rudnick,
Proceedings of the European Test Workshop, May 2000.

FreezeFrame: Compact test generation using a frozen clock strategy,
Yanti Santoso, Matthew Merten, Elizabeth M. Rudnick, and Miron Abramovici,
Proceedings of the Design, Automation and Test in Europe Conference (DATE), pp. 747-752, March 1999.

Fast static compaction algorithms for sequential circuit test vectors,
Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel,
IEEE Transactions on Computer-Aided Design, vol. 48, no. 3, pp. 311-322, March 1999.

Efficient techniques for dynamic test sequence compaction,
Elizabeth M. Rudnick and Janak H. Patel,
IEEE Transactions on Computer-Aided Design, vol. 48, no. 3, pp. 323-330, March 1999.

Test Set Compaction Algorithms for Combinational Circuits
Ilker Hamzaoglu and Janak H. Patel,
Proceedings of the International Conference on Computer-Aided Design, November 1998.

Enhancing topological ATPG with high-level information and symbolic techniques,
Fulvio Corno, Janak H. Patel, Elizabeth M. Rudnick, Matteo Sonza Reorda, and Roberto Vietti,
Proceedings of the International Conference on Computer Design, October 1998.

Compact Two-Pattern Test Set Generation for Combinational and Full Scan Circuits
Ilker Hamzaoglu and Janak H. Patel,
Proceedings of the International Test Conference, October 1998.

New Techniques for Deterministic Test Pattern Generation
Ilker Hamzaoglu and Janak H. Patel,
Proceedings of the VLSI Test Symposium, pp. 446-452, April 1998.

Application of genetically-engineered finite-state-machine sequences to sequential circuit ATPG,
Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel,
IEEE Transactions on Computer-Aided Design, vol. 17, no. 3, pp. 239-254, March 1998.

Fast sequential circuit test generation using high-level and gate-level techniques,
Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis, Fulvio Corno, Paulo Prinetto, and Matteo Sonza Reorda,
Proceedings of the Design, Automation and Test in Europe Conference (DATE), pp. 570-576, February 1998.

Putting the squeeze on test sequences,
Elizabeth M. Rudnick and Janak H. Patel,
Proceedings of the International Test Conference, pp. 723-732, November 1997.

BART: A bridging fault test generator for sequential circuits,
James P. Cusey and Janak H. Patel,
Proceedings of the International Test Conference, pp. 838-847, November 1997.

A genetic algorithm framework for test generation,
Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, and Thomas M. Niermann,
IEEE Transactions on Computer-Aided Design, vol. 16, no. 9, pp. 1034-1044, Sept. 1997.

Static logic implication with application to redundancy identification,
Jian-Kun Zhao, Elizabeth M. Rudnick, and Janak H. Patel,
Proceedings of the VLSI Test Symposium, pp. 288-293, April 1997.

Fast algorithms for static compaction of sequential circuit test vectors,
Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel,
Proceedings of the VLSI Test Symposium, pp. 188-195, April 1997.

Sequential circuit test generation using dynamic state traversal,
Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel,
Proceedings of the European Design and Test Conference, pp. 22-28, March 1997.

Parallel genetic algorithms for simulation-based sequential circuit test generation,
Dilip Krishnaswamy, Michael S. Hsiao, V. Saxena, Elizabeth M. Rudnick, Janak H. Patel, and Prithviraj Banerjee,
Proceedings of the International Conference on VLSI Design, pp. 475-481, January 1997.

Simulation-based techniques for dynamic test sequence compaction,
Elizabeth M. Rudnick and Janak H. Patel,
Proceedings of the International Conference on Computer-Aided Design, November 1996.

Automatic test generation using genetically engineered distinguishing sequences,
Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel,
Proceedings of the VLSI Test Symposium, pp. 216-223, April 1996.
Abstract

Alternating strategies for sequential circuit ATPG,
Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel,
Proceedings of the European Design and Test Conference, pp. 368-374, March 1996.
Abstract

State justification using genetic algorithms in sequential circuit test generation,
Elizabeth M. Rudnick and Janak H. Patel,
Coordinated Science Laboratory, University of Illinois, Urbana, IL,
Technical Report CRHC-96-01/UILU-ENG-96-2201,
January 1996.
Abstract

Combining deterministic and genetic approaches for sequential circuit test generation
Elizabeth M. Rudnick and Janak H. Patel,
Proceedings of the ACM/IEEE Design Automation Conference,
pp. 183-188, June 1995.
Abstract

High level test generation using software metrics,
Mark W. Johnson
M.S. thesis, Department of Electrical and Computer Engineering, Technical Report CRHC-95-06/UILU-ENG-95-2204,
University of Illinois, February 1995.
Abstract

A genetic approach to test application time reduction for full scan and partial scan circuits,
Elizabeth M. Rudnick and Janak H. Patel,
Proceedings of the Eighth International Conference on VLSI Design, pp. 288-293, January 1995.
Abstract

Architectural level test generation for microprocessors,
Jaushin Lee and Janak H. Patel,
IEEE Transactions on Computer-Aided Design of Circuits and Systems, vol. 13, no. 10, pp. 1288-1300, October 1994.
Abstract

Simulation-based techniques for sequential circuit testing,
Elizabeth M. Rudnick,
Ph.D. dissertation, Department of Electrical and Computer Engineering, Technical Report CRHC-94-14/UILU-ENG-94-2229,
University of Illinois, August 1994.
Abstract

Sequential circuit test generation in a genetic algorithm framework,
Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, and Thomas M. Niermann,
Proceedings of the ACM/IEEE Design Automation Conference, pp. 698-704, June 1994.
Abstract

ProperHITEC: A portable, parallel, object-oriented approach to sequential circuit test generation,
Steven Parkes, Prithviraj Banerjee, and Janak H. Patel, Proceedings of the ACM/IEEE Design Automation Conference, pp. 717-721, June 1994.
Abstract

Application of simple genetic algorithms to sequential circuit test generation,
Elizabeth M. Rudnick, John G. Holm, Daniel G. Saab, and Janak H. Patel,
Proceedings of the European Design and Test Conference, pp. 40-45, February 1994.
Abstract

An architectural level test generator based on non-linear equaltion solving,
Jaushin Lee and Janak H. Patel,
Journal of Electronic Testing, vol. 4, no. 2, pp. 137-150, 1993.
Abstract

Theory and practice of sequential machine testing and testability,
Irith Pomeranz, Sudhakar M. Reddy, and Janak H. Patel,
Proceedings of the International Symposium on Fault Tolerant Computing, pp. 330-337, June 1993.

Efficient variable ordering heuristics for shared ROBDD,
Pi-Yu Chung, Ibrahim N. Hajj, and Janak H. Patel,
International Symposium on Circuits and Systems, pp. 1690-1693, 1993.
Abstract

Fault ordering in sequential automatic test pattern generation,
Scott M. Heydinger,
M.S. thesis, Department of Electrical and Computer Engineering, Technical Report CRHC-93-02/UILU-ENG-93-2202,
University of Illinois, January 1993.
Abstract

Automatic test generation for linear digital systems with bi-level search using matrix transform methods,
R. K. Roy, A. Chatterjee, J. H. Patel, J. A. Abraham, and M. A. d'Abreu,
International Conference on Computer-Aided Design, pp. 224-228, November 1992.
Abstract

An instruction sequence assembling methodology for testing microprocessors,
Jaushin Lee and Janak H. Patel,
Proceedings of the International Test Conference, pp. 49-58, September 1992.
Abstract

Architectural level test generation and fault simulation,
Jaushin Lee,
Ph.D. dissertation, Department of Electrical and Computer Engineering,
Technical Report CRHC-92-20,
University of Illinois, August 1992.

Hierarchical test generation under intensive global functional constraints,
Jaushin Lee and Janak H. Patel,
Proceedings of the ACM/IEEE Design Automation Conference, pp. 261-266, June 1992.

Test compaction for sequential circuits,
Thomas M. Niermann, R. K. Roy, Janak H. Patel, and Jacob A. Abraham,
IEEE Transactions on Computer-Aided Design of Circuits and Systems, vol. 11, no. 2, pp. 260-267, February 1992.
Abstract

A signal-driven discrete relaxation technique for architectural level test generation,
Jaushin Lee and Janak H. Patel,
Proceedings of the International Conference on Computer-Aided Design, pp. 458-461, November 1991.

ARTEST: An architectural level test generator for data path faults and control faults,
Jaushin Lee and Janak H. Patel,
Proceedings of the International Test Conference, pp. 729-738, October 1991.

An architectural level test generator for a hierarchical design environment,
Jaushin Lee and Janak H. Patel,
Proceedings of the 21st Symposium on Fault-Tolerant Computing, pp. 44-51, June 1991.

Parallel test generation for sequential circuits on general purpose multiprocessors,
Srinivas Patil, Prithviraj Banerjee, and Janak H. Patel,
Proceedings of the ACM/IEEE Design Automation Conference, pp. 155-159, June 1991.

Techniques for sequential circuit automatic test generation,
Thomas M. Niermann,
Ph.D. dissertation, Department of Electrical and Computer Engineering,
Technical Report CRHC-91-8/UILU-ENG-91-2214,
University of Illinois, March 1991.

HITEC: A test generation package for sequential circuits,
Thomas M. Niermann and Janak H. Patel,
Proceedings of the European Conference on Design Automation (EDAC), pp. 214-218, February 1991.
Abstract

High-level methodologies for test generation and logic simulation,
Utpal J. Dave,
M.S. thesis, Department of Electrical and Computer Engineering,
Technical Report CSG-114/UILU-ENG-89-2238,
University of Illinois, 1989.

A functional-level test generation methodology using two-level representations,
Utpal J. Dave and Janak H. Patel,
Proceedings of the ACM/IEEE Design Automation Conference, pp. 722-725, June 1989.

Techniques to speedup test generation for VLSI circuits,
Susheel J. Chandra,
Ph.D. dissertation, Department of Electrical and Computer Engineering,
Technical Report CSG-109/UILU-ENG-89-2232,
University of Illinois, 1989.

Concurrent automatic test generation for delay faults,
Thomas M. Niermann,
M.S. thesis, Department of Electrical and Computer Engineering,
Technical Report CSG-102/UILU-ENG-89-2213,
University of Illinois, 1989.

Compaction of ATPG-generated test sequences for sequential circuits,
R. K. Roy, Thomas M. Niermann, Janak H. Patel, Jacob A. Abraham, and Resve A. Saleh,
Proceedings of the International Conference on Computer-Aided Design, pp. 382-384, November 1988.

Testing and fault-tolerance aspect of high density VLSI memory,
Pinaki Mazumder,
Ph.D. dissertation, Department of Electrical Engineering,
Technical Report CSG-81/UILU-ENG-88-2206,
University of Illinois, 1988.

Test generation in a parallel processing environment,
Susheel Chandra and Janak H. Patel,
Proceedings of the International Conference on Computer Design, pp. 11-14, October 1988.

A hierarchical approach to test vector generation,
Susheel J. Chandra and Janak H. Patel,
Proceedings of the ACM/IEEE Design Automation Conference, pp. 495-501, June 1987.

Parallel testing for pattern sensitive faults in semiconductor random access memory,
Pinaki Mazumder and Janak H. Patel,
Technical Report CSG-56/UILU-ENG-86-2232,
University of Illinois, 1986.

Development of an automatic test pattern generation package,
Sanjaykumar T. Patel,
M.S. thesis, Department of Electrical Engineering,
Technical Report CSG-45/UILU-ENG-85-2224,
University of Illinois, 1985.

Algorithms for minimizing test sets for CMOS VLSI circuits,
Charles J. Stancil,
M.S. thesis, Department of Electrical Engineering,
Technical Report CSG-42,
University of Illinois, 1985.