IGATE Design Verification

University of Illinois, Urbana, IL

Detection of all possible errors which can be made in the process of microprocessor design is an intractable problem. The goals of this project are to develop new techniques and algorithms for automatic test program generation with the twin aims of increasing coverage of all possible design errors and reducing test application time.

Key Contributors

• Elizabeth Rudnick
• Mrinal Bose
• Liyang Lai
• Xiaojun Ma
• Ta-Chung Chang

Software

• BITG_ARM : A biased random instruction generator and simulator for the ARM7 processor core.
• BITG_DLX : A biased random instruction generator and simulator for the DLX benchmark proccessor.
• SwiftBias: An automatic bias sequence generation tool targeted for the PowerPC.
• STATECOV: An automatic bias sequence generation tool targeted for BITG_ARM and BITG_DLX.

Benchmarks

• arm7_Verilog, Version 1.0: An ARM7 processor core in Verilog HDL. The ARM7 core was developed by students in ECE 371EMR during the Spring 2000 semester. The code has been compiled into a single directory and cleaned up to some extent, but some bugs may remain. The current version is compatible with BITG-ARM and simulates correctly for the test case provided. Documentation is brief:
• Memory Interface Documentation
• ARM7 Core Documentation
• verification/dlx.tar.gz The DLX benchmark processor in VHDL.

Research Papers

• M. Bose, E. M. Rudnick, and M. Abadir, "Automatic bias generation using pipeline instruction state coverage for biased random instruction generation," Proc. Int. On-Line Testing Workshop, July 2001.
• M. Bose, J. Shin, E. M. Rudnick, T. Dukes, and M. Abadir, "A genetic approach to automatic bias generation for biased random instruction generation," Proc. Congress on Evolutionary Computation, May 2001.
• T.-C. Chang, V. Iyengar, and E. M. Rudnick, "A biased random instruction generation environment for architectural verification of pipelined processors," J. of Electronic Testing, Theory and Applications (JETTA), vol. 16, nos. 1/2, pp. 13-27, Feb./Apr. 2000.
• T.-C. Chang and E. M. Rudnick, "A design verification environment for pipelined microprocessors", Proc. Int. Workshop on Microprocessor Test and Verification (MTVW), Oct. 1998.