c=> Seed = 5
c=> OutFile = and10.out
c=> LstFile = and10.lst
c=> TraceFile = and10.trace
c=> InstMemFile = and10.imem
c=> DataMemFile = and10.dmem
c=> RegistersRefFile = and10.regsr
c=> DataMemRefFile = and10.dmemr
c=> CovFile = and10.cov
c=> LstOrder = sequential
c=> ShiftLst allshifts = { 0, 12 , 13, 15 }
c=> ImmLst nwimm = { 0:3, 5:9, 15 }
c=> ImmLst aconds = { 0:3, 5:9, 15 }
c=> RotateLst allrots = {0:15, 40:60 }
c=> ShiftTypeLst alltypes = {0:3}
c=> RegLst reglow = { r0, r1,r2 }
c=> DefShiftSupType = 1
c=> DefRegorImm = 1
c=> DefShift  = allshifts
c=> DefSetCond  = 1
c=> InstLst branch = {b,bl}
c=> InstLst dp = {and,eor,sub,rsb,add,adc,sbc,rsc,tst,teq,cmp,cmn,orr,
mov,bic,mvn}
c=> InstLst mults = {mul,mla}
c=> InstLst sdt = {ldr,str}
c=> InstLst fpu = {cdp,ldc,stc,mrc,mcr}
c=> InstLst arm = {b,bl,and,eor,sub,rsb,add,adc,sbc,rsc,tst,teq,cmp,cmn,
orr,mov,bic,cmn,mul,mla,ldr,str,swp,swi}
c=> InstLst armfpu = {b,bl,and,eor,sub,rsb,add,adc,sbc,rsc,tst,teq,cmp,
cmn,orr,mov,bic,cmn,mul,mla,ldr,str,swp,swi,cdp,ldc,stc,mrc,mcr}
c=> InstPerTest = 10
c=> Gen and
c=> InstStartAddr = 0x104
c=> InstEndAddr = 0x200
c=> DataStartAddr = 0x6000
c=> DataMemStart = 0x4000
c=> DataMemEnd = 0x7fff
c=> InstMemStart = 0x0
c=> InstMemEnd = 0x3fff
c=> MemOffset = 0x6000