This research describes a hardware test platform and test methodology
that was developed for NASA’s Electronic Parts and Packaging
Program. Nonvolatile memories will play an increasingly important role
in future NASA missions. Autonomous systems require nonvolatile
memories to store the system’s states, programs, and data, and the
limited bandwidth of communication during distant missions also makes
reliable nonvolatile memory storage a necessity. A test bench has been
developed for testing memory chips from various nonvolatile memory
technologies, using a Xilinx XC4010E (10,000 gate) FPGA. The test
bench is being used to perform endurance, reliability, and MINVDD
testing. A MATS+ memory test, which can detect address decoder faults
and stuck-at faults and cycles through all the addresses in the
memory, was chosen for reliability testing. For endurance testing,
specific data patterns are written to and read from the same address
range of the memory continuously, which allows for faster endurance
testing, especially when slower memory technologies are used. In
MINVDD testing, the minimum supply voltage at which a chip can
function correctly is determined. This information is then used to
screen out “weak” chips. In all of these tests, the data logged
upon each error includes the error number, the address at which the
error occurred, the cycle number (where one cycle is defined as one
read or write operation to a single address), the incorrect data value
read, and (for the MATS+ test) the portion of the test in which the
error occurred. This test bench offers several advantages over
commercial testers when used for reliability and endurance
testing. Endurance testing to a chip's specifications could involve
more than 1010 read/write cycles, which can take up to 28 days for the
Ramtron FM24C04 serial FRAM. Commercially available memory testers
with high hourly rates may prove extremely expensive for testing
nonvolatile memories with 1012 to 1015 read/write cycles. In
comparison, the FPGA-based testers are inexpensive and more flexible.
If several FPGA boards are used, many chips can be tested
simultaneously at a fraction of the cost compared to the commercial
testers. No errors have been found in reliability, endurance, or
MINVDD testing on any of the memories tested.