The research is targeted to develop effective techniques for (1)
sequential circuit test generation for fault detection and diagnosis
and (2) design for testability (DFT). First, two DFT techniques based
on clock partitioning and clock freezing are proposed to ease the test
generation process. In one DFT technique, a circuit is mapped into
various pipeline configuration.  In the other DFT technique, a circuit
is reduced to a pipe without any global feedback loops. Two
opportunistic algorithms are proposed for test generation. Second, a
low-power logic built-in self-test technique, also based on clock
partitioning and clock freezing, is proposed for transition fault
testing.  Similarly, a circuit is configured into various pipes
without global feedback loops, and pseudorandom vectors are applied to
target transition faults. Third, a symbolic/genetic hybrid approach is
proposed for sequential circuit test generation. A circuit is
structurally divided into a controller and a datapath.  Symbolic
techniques are used to target faults in the controller, and genetic
algorithms (GAs) are used for the datapath.  Finally, a GA-based
diagnostic test generation approach is proposed for sequential
circuits. A simple GA is used to target groups of undistinguished
faults iteratively.  Experimental results have demonstrated the
efficiency of the proposed techniques.