Center for Reliable and High-Performance Computing The University of Illinois at Urbana-Champaign
The Unconventional Computer Architecture group focuses on architectures that do not follow the stored-program paradigm common in today's computer systems. Our interests include physical implementations of computation such as reconfigurable logic, integration of unconventional computing devices with conventional processors, and computing using non-silicon devices. The UCA group's work is part of the ongoing research being performed at the Center for Reliable and High-Performance Computing. We are located in the Coordinated Science Laboratory located on the University of Illinois at Urbana-Champaign campus.

Current Projects:

• Intelligent Queues -- a Design Abstraction for Heterogeneous Systems
• Magnetoelectronic Gates

Previous Projects: (or projects that are ongoing but winding down):

• Amalgam -- a Clustered Programmable-Reconfigurable Processor
• Memory-Efficient EPIC Processors

Professor:

• Nicholas Carter (npcarter@crhc.uiuc.edu)

Graduate Students:

• Jeffrey J. Cook ()
• Derek B. Gottlieb ()
• Krzysztof Kieltyka ()
• Erica Lundgren ()
• Brian Moschel ()
• Nitin Navale ()

Alumni:

• James E. Simon - MS, May 2005
• Love Kothari - MS, May 2005
• Chi-Wei Wang - MS, January 2005
• Richard B. Kujoth - MS, August 2004
• Azmat Hussain - MS, June 2004
• Jeffrey M. Stine - MS, June 2004
• Steven P. Ferrera - MS, March 2004
• Smitha L. Rapaka - MS, August 2002
• Joshua D. Walstrom - MS, July 2002
• John T. Strasser - MS, January 2002
• Jim T. Y. Fung - MS, December 2000

Publications:

Articles in Journals:

• A Magnetoelectronic Register File Cell for a Self-Checkpointing Microprocessor [PDF]
  Nitin Navale, Erica Lundgren, and Nicholas P. Carter.
  To appear in International Journal of Circuit Theory and Applications, 2007
  
  
• Architecture of a Self-Checkpointing Microprocessor that Incorporates Nanomagnetic Devices [PDF]
  Love Kothari and Nicholas P. Carter.
  To appear in IEEE Transactions on Computers, 2007
  
  
• A Wire Delay-Tolerant Reconfigurable Unit for a Clustered Programmable-Reconfigurable Processor [PDF]
  Richard B. Kujoth, Chi-Wei Wang, Jeffrey J. Cook, Derek B. Gottlieb, and Nicholas P. Carter.
  To appear in Journal of Microprocessors and Microsystems, 2007
  
  
• Modeling Wire Delay, Area, Power, and Performance in a Simulation Infrastructure [PDF]
  Azmat Hussain and Nicholas P. Carter.
  In IBM Journal of Research and Development, April 2006
  
  
• Gated Hybrid Hall Effect Device on Silicon [PDF]
  Pratyush D. Konungo, Alexandra Imre, Bin Wu, Alexi O. Orlov, Geregory L. Snider, Wolfgang Porod, and Nicholas P. Carter
  In Microelectronics Journal, 2005.
  
  
• Reconfigurable Magnetoelectronic Circuits for Threshold Logic [PDF]
  Steve P. Ferrera and Nicholas P. Carter.
  In International Journal of Circuit Theory and Applications, November 2004
  
  
• Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction [PDF]
  Jeffrey Stine and Nicholas P. Carter
  In Computer Architecture Letters, 2004.
  
  

Articles in Conference Proceedings:

• Hall-Effect Circuits and Architectures for Non-Volatile System Design [PDF]
  Nicholas P. Carter, Steven Ferrera, Love Kothari, and Stanley Ye
  In Proceedings of the 17th European Conference on Circuit Theory and Design. August 2005.
  
  
• Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor [PDF]
  Chi-Wei Wang, Nicholas P. Carter, Richard B. Kujoth, Jeffrey J. Cook, and Derek B. Gottlieb
  In Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL). August 2005.
  
  
• Gated Hybrid Hall Effect Device on Silicon
  Pratyush D. Konungo, Alexandra Imre, Bin Wu, Alexi O. Orlov, Geregory L. Snider, Wolfgang Porod, and Nicholas P. Carter
  In 5th International Conference on Low Dimensional Structures and Devices. December 2004.
  
  
• Modeling Wire Delay, Area, Power, and Performance in a Simulation Infrastructure [PDF]
  Azmat Hussain and Nicholas P. Carter.
  In First Watson Conference on Interaction Between Architecture, Circuits, and Compilers (P=ac²), October 2004
  
  
• Magnetoelectronic Structures for Non-Volatile Microprocessors
  Nicholas P. Carter and Steven P. Ferrera.
  In Wild and Crazy Ideas Session, 2004 International Conference on Architectural Support for Programming Languages and Operating Systems.
  
  
• A Magnetoelectronic Macrocell Employing Reconfigurable Threshold Logic [PDF]
  Steve P. Ferrera and Nicholas P. Carter.
  In Proceedings of the 12th ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2004
  
  
• A Reconfigurable Unit for a Clustered Programmable-Reconfigurable Processor [PDF]
  Richard B. Kujoth, Chi-Wei Wang, Derek B. Gottlieb, Jeffrey J. Cook, Nicholas P. Carter.
  In Proceedings of the 12th ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2004.
  
  
• Mapping Computation Kernels to Clustered Programmable-Reconfigurable Processors [PDF]
  Jeffrey J. Cook, Lee W. Baugh, Derek B. Gottlieb, Nicholas P. Carter.
  Extended Abstract in Proceedings of the 2nd IEEE International Conference on Field Programmable Technology (FPT), December 2003.
  
  
• Reconfigurable Circuits Using Hybrid Hall Effect Devices [PDF]
  Steve P. Ferrera, Nicholas P. Carter.
  In Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), September 2003.
  
  
• AmalGUI: A User Interface for a Clustered Programmable-Reconfigurable Processor Simulator [PDF] [PS]
  Chi-Wei Wang, Derek B. Gottlieb, Jeffrey J. Cook, Nicholas P. Carter.
  In Proceedings of the 10th Annual Tcl/Tk Conference, July 2003.
  
  
• Hybrid Hall Effect Devices -- A Novel Building Block for Reconfigurable Logic [PDF]
  Steve Ferrera and Nicholas P. Cater
  In Second Workshop on Non-Silicon Computation, June 2003.
  
  
• Microprocessor Interfacing Laboratory [PDF] [PS]
  Derek B. Gottlieb, Nicholas P. Carter.
  In Proceedings of the 2003 International Conference on Microelectronic Systems Education (MSE 2003), June 2003.
  
  
• Clustered Programmable-Reconfigurable Processors [PDF] [PS]
  Derek B. Gottlieb, Jeffrey J. Cook, Joshua D. Walstrom, Steven Ferrera, Chi-Wei Wang, Nicholas P. Carter.
  In Proceedings of the 1st IEEE International Conference on Field Programmable Technology (FPT), December 2002.
  
  
• Mapping Algorithms to the Amalgam Programmable-Reconfigurable Processor [PDF] [PS]
  Jeffrey J. Cook, Derek B. Gottlieb, Joshua D. Walstrom, Steven Ferrera, Chi-Wei Wang, Nicholas P. Carter.
  Extended Abstract in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), April 2002.
  
  
• The Design of the Amalgam Reconfigurable Cluster [PDF] [PS]
  Joshua D. Walstrom, Jeffrey J. Cook, Derek B. Gottlieb, Steven Ferrera, Chi-Wei Wang, Nicholas P. Carter.
  Extended Abstract in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), April 2002.
  

Presentations:

• A Reconfigurable Unit for a Clustered Programmable-Reconfigurable Processor [PDF]
  Slides from the presentation at FPGA'04, February 2004.
  
  
• Microprocessor Interfacing Laboratory [PDF]
  Poster from the presentation at MSE'03, June 2003.
  
  
• Clustered Programmable-Reconfigurable Processors [PDF] [PS]
  Slides from the presentation at FPT'02, December 2002.
  

Theses:

• Global Dynamic Voltage Scaling for On-Chip Networks [PDF] [PS]
  James E. Simon
  Master's Thesis, University of Illinois at Urbana-Champaign, May 2005.
  
  
• The Design of a Nonvolatile Processor using Magnetoelectronic Devices [PDF] [PS]
  Love Kothari
  Master's Thesis, University of Illinois at Urbana-Champaign, April 2005.
  
  
• Employing Pipelining to Tolerate Wire Latencies in a Clustered Programmable-Reconfigurable Processor [PDF] [PS]
  Chi-Wei Wang
  Master's Thesis, University of Illinois at Urbana-Champaign, January 2005.
  
  
• Circuit Design and Study of the Amalgam Reconfigurable Cluster [PDF]
  Richard B. Kujoth
  Master's Thesis, University of Illinois at Urbana-Champaign, August 2004.
  
  
• The Amalgam Compiler Infrastructure [PDF] [PS]
  Jeffrey J. Cook
  Master's Thesis, University of Illinois at Urbana-Champaign, August 2004.
  
  
• Memory Hierarchy and Network Design Tradeoffs for Clustered Processors [PDF] [PS]
  Derek B. Gottlieb
  Master's Thesis, University of Illinois at Urbana-Champaign, August 2004.
  
  
• Power and Interconnect Analysis in Very Long Instruction Word Architectures [PS]
  Azmat Hussain
  Master's Thesis, University of Illinois at Urbana-Champaign, June 2004.
  
  
• Techniques for Reducing Link Power in On-Chip Networks [PS]
  Jeffrey M. Stine
  Master's Thesis, University of Illinois at Urbana-Champaign, June 2004.
  
  
• Reconfigurable Circuit Designs and Applications for Magnetoelectronic Logic [PDF]
  Steve P. Ferrera
  Master's Thesis, University of Illinois at Urbana-Champaign, May 2004.
  
  
• Performance Modeling of the Memory-Efficient EPIC Architecture [PDF]
  Smitha L. Rapaka
  Master's Thesis, University of Illinois at Urbana-Champaign, August 2002.
  
  
• The Design of the Amalgam Reconfigurable Cluster [PS]
  Joshua D. Walstrom
  Master's Thesis, University of Illinois at Urbana-Champaign, July 2002.
  
  
• Evaluation of Branch Prediction on Processor Energy Consumption [PDF] [PS]
  John T. Strasser
  Master's Thesis, University of Illinois at Urbana-Champaign, January 2002.
  
  
• A Simulation Framework for Analysis and Optimization of Sharing Patterns on CC-NUMA Shared Memory Systems [PDF] [PS]
  Jim T. Y. Fung
  Master's Thesis, University of Illinois at Urbana-Champaign, December 2000.